JAJSP50A May   2023  – September 2023 AMC131M03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 Temperature Sensor
        1. 8.3.15.1 Internal Temperature Sensor
        2. 8.3.15.2 External Temperature Sensor
        3. 8.3.15.3 Clock Selection for Temperature Sensor Operation
      16. 8.3.16 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M03-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.9 Clocking and Power Modes

An LVCMOS clock must be provided at the CLKIN pin continuously when the AMC131M03-Q1 is running in normal operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a tradeoff between power consumption and dynamic range.

The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of two power modes: high-resolution (HR) or low-power (LP) mode. Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow the guidance provided in the Recommended Operating ConditionsRecommended Operating Conditions table corresponding to the intended power mode for the device to perform according to the specification.

The main clock must be externally provided at the CLKIN pin. As shown in Figure 8-5, a user-programmable clock divider divides the main clock to derive the internal modulator clock (MOD_CLK). By default, the main clock provided at the CLKIN pin is divided by NDIV = 2 to generate a 50% duty cycle internal modulator clock. As listed in Table 8-8, the divider ratio NDIV can be changed to values of 4, 8, and 12 using the CLK_DIV[1:0] bits in the CLOCK register.

GUID-20211222-SS0I-DJTF-BZ1R-W4STTF4C1NCM-low.svg Figure 8-5 Programmable Clock Divider Block Diagram
Table 8-2 Modulator Clock Divider Selection
CLK_DIV[1:0] NDIV FOR MOD_CLK AT ALL CHANNELS
00b 2
01b 4
10b 8
11b 12

The clock frequency range of the internal DC/DC converter must be synchronized with the modulator clock to minimize interference. To optimize the DC/DC converter internal clock, the actual frequency value of the modulator clock must be written to the DCDC_CTRL register immediately after device power-up. The modulator clock frequency is a result of the frequency provided at the CLKIN pin and the selected divider ratio (for example, if a 4-MHz clock frequency is provided at the CLKIN pin, and the divider ratio is set to 4, then the frequency of the modulator clock MOD_CLK is 1 MHz). The correct modulator clock frequency value must be configured in the DCDC_CTRL register, as given in Table 8-3, by writing to the DCDC_FREQ[3:0] register bits immediately after start-up.

An example calculation is:

  • Main clock: fCLKIN = 8.192 MHz
  • Divider ratio: NDIV= 4
  • Resulting modulator clock: fCLKIN / NDIV = 2.048 MHz
  • Modulator clock frequency is within the range: 1.926 MHz to 2.051 MHz; see Table 8-3
  • Required DCDC_FREQ[3:0] bit setting: 1000b; see Table 8-3

Table 8-3 Modulator Clock Frequency Range Selection for DC/DC Synchronization
MODULATOR CLOCK FREQUENCY (MHz) DCDC_FREQ[3:0] BIT SETTING
3.768 MHz to 4.100 MHz 0000b
3.366 MHz to 3.768 MHz 0001b
3.041 MHz to 3.366 MHz 0010b
2.773 MHz to 3.041 MHz 0011b
2.549 MHz to 2.773 MHz 0100b
2.358 MHz to 2.549 MHz 0101b
2.194 MHz to 2.358 MHz 0110b
2.051 MHz to 2.194 MHz 0111b
1.926 MHz to 2.051 MHz 1000b
1.815 MHz to 1.926 MHz 1001b
1.716 MHz to 1.815 MHz 1010b
1.627 MHz to 1.716 MHz 1011b
1.547 MHz to 1.627 MHz 1100b
1.475 MHz to 1.547 MHz 1101b
1.409 MHz to 1.475 MHz 1110b
1.400 MHz to 1.409 MHz 1111b