JAJSP50A May   2023  – September 2023 AMC131M03-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 Temperature Sensor
        1. 8.3.15.1 Internal Temperature Sensor
        2. 8.3.15.2 External Temperature Sensor
        3. 8.3.15.3 Clock Selection for Temperature Sensor Operation
      16. 8.3.16 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M03-Q1 Registers
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Channel Phase Calibration

The AMC131M03-Q1 allows fine adjustment of the sample phase between channels by using channel phase calibration. This feature is helpful when different channels are measuring the outputs of different types of sensors that have different phase responses. For example, in power metrology applications, voltage can be measured by a voltage divider, whereas current is measured using a current transformer that exhibits a phase difference between the input and output signals. The differences in phase between the voltage and current measurement must be compensated to measure the power and related parameters accurately.

The phase setting of the different channels is configured by the PHASEn[9:0] bits in the CHn_CFG register corresponding to the channel whose phase adjustment is desired. The register value is a 10-bit, two's-complement value corresponding to the number of modulator clock cycles of phase offset compared to a reference phase of zero degrees.

The mechanism for achieving phase adjustment derives from the ΔΣ architecture. The ΔΣ modulator produces samples continuously at the modulator frequency, fMOD. These samples are filtered and decimated to the output data rate by the digital filter. The ratio between fMOD and the data rate is the oversampling ratio (OSR). Each conversion result corresponds to an OSR number of modulator samples provided to the digital filter. When the different channels of the AMC131M03-Q1 have no programmed phase offset between them, the modulator clock cycles corresponding to the conversion results of the different channels are aligned in the time domain. Figure 8-11 shows an example scenario where the voltage input to channel 1 has no phase offset from channel 0.

GUID-55F97015-F426-48A2-9AC1-336BC199E175-low.gifFigure 8-11 Two Channel Outputs With Equal Phase Settings

However, the sample period of one channel can be shifted with respect to another. If the inputs to both channels are sinusoids of the same frequency and the samples for these channels are retrieved by the host at the same time, the effect is that the phase of the channel with the modified sample period appears shifted. Figure 8-12 shows how the period corresponding to the samples are shifted between channels. Figure 8-13 illustrates how the samples appear as having generated a phase shift when retrieved by the host.

GUID-678E6782-9027-4FCF-A60A-71669BD563D9-low.gifFigure 8-12 Channel 1 With a Positive Sample Phase Shift With Respect to Channel 0
GUID-1B559A10-EFC9-4F87-BA7F-D02ABAB5EF8F-low.gifFigure 8-13 Channels 1 and 0 From the Perspective of the Host

The valid setting range is from –OSR / 2 to (OSR / 2) – 1, except for OSRs greater than 1024, where the phase calibration setting is limited to –512 to 511. If a value outside of –OSR / 2 and (OSR / 2) – 1 is programmed, the device internally clips the value to the nearest limit. For example, if the OSR setting is programmed to 128 and the PHASEn[9:0] bits are programmed to 0001100100b corresponding to 100 modulator clock cycles, the device sets the phase of the channel to 63 because that value is the upper limit of phase calibration for that OSR setting. Table 8-6 gives the range of phase calibration settings for various OSR settings.

Table 8-6 Phase Calibration Setting Limits for Different OSR Settings
OSR SETTING PHASE OFFSET RANGE (tMOD) PHASEn[9:0] BITS RANGE
64 –32 to 31 11 1110 0000b to 00 0001 1111b
128 –64 to 63 11 1100 0000b to 00 0011 1111b
256 –128 to 127 11 1000 0000b to 00 0111 1111b
512 –256 to 255 11 0000 0000b to 00 1111 1111b
1024 –512 to 511 10 0000 0000b to 01 1111 1111b
2048 –512 to 511 10 0000 0000b to 01 1111 1111b
4096 –512 to 511 10 0000 0000b to 01 1111 1111b
8192 –512 to 511 10 0000 0000b to 01 1111 1111b
16384 –512 to 511 10 0000 0000b to 01 1111 1111b

Follow these steps to create a phase shift larger than half the sample period for OSRs less than 2048:

  • Create a phase shift corresponding to an integer number of sample periods by modifying the indices between channel data in software
  • Use the phase calibration function of the AMC131M03-Q1 to create the remaining fractional sample period phase shift
For example, to create a phase shift of 2.25 samples between channels 0 and 1, create a phase shift of two samples by aligning sample N in the channel 0 output data stream with sample N+2 in the channel 1 output data stream in the host software. Make the remaining 0.25 sample adjustment using the AMC131M03-Q1 phase calibration function.

The phase calibration settings of the channels affect the timing of the data-ready interrupt signal, DRDY. See the Data Ready (DRDY) section for more details regarding how phase calibration affects the DRDY signal.