JAJSK09B November   2014  – September 2020 CC3100MOD

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 機能ブロック図
  5. 機能ブロック図
  6. Revision History
  7. Terminal Configuration and Functions
    1. 7.1 CC3100MOD Pin Diagram
    2. 7.2 Pin Attributes
      1.      10
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Consumption Summary
    6. 8.6  TX Power and IBAT versus TX Power Level Settings
    7. 8.7  Brownout and Blackout Conditions
    8. 8.8  Electrical Characteristics (3.3 V, 25°C)
    9. 8.9  WLAN RF Characteristics
      1. 8.9.1 WLAN Receiver Characteristics
      2. 8.9.2 WLAN Transmitter Characteristics
    10. 8.10 Reset Requirement
    11. 8.11 Thermal Resistance Characteristics for MOB Package
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1 Wake-Up Sequence
      2. 8.12.2 Wake Up From Hibernate
        1. 8.12.2.1 nHIB Timing Requirements #GUID-400CF46C-B651-457D-A1D7-C5F78DD51018/SWRS1661423
      3. 8.12.3 Interfaces
        1. 8.12.3.1 Host SPI Interface Timing
        2. 8.12.3.2 SPI Host Interface
    13. 8.13 Host UART
      1. 8.13.1 5-Wire UART Topology
      2. 8.13.2 4-Wire UART Topology
      3. 8.13.3 3-Wire UART Topology
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Module Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
      3. 9.2.3 Host Interface and Driver
      4. 9.2.4 System
    3. 9.3 Functional Block Diagram
    4. 9.4 Wi-Fi Network Processor Subsystem
    5. 9.5 Power-Management Subsystem
      1. 9.5.1 VBAT Wide-Voltage Connection
    6. 9.6 Low-Power Operating Modes
      1. 9.6.1 Low-Power Deep Sleep
      2. 9.6.2 Hibernate
  10. 10Applications, Implementation, and Layout
    1. 10.1 Reference Schematics
    2. 10.2 Design Requirements
    3. 10.3 Layout Recommendations
      1. 10.3.1 RF Section (Placement and Routing)
      2. 10.3.2 Antenna Placement and Routing
      3. 10.3.3 Transmission Line Considerations
  11. 11Environmental Requirements and Specifications
    1. 11.1 Temperature
      1. 11.1.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Firmware Updates
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Package Option
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • MOB|63
サーマルパッド・メカニカル・データ
発注情報

Revision History

Changes from December 6, 2014 to September 22, 2020 (from Revision A () to Revision B ())

  • 文書全体にわたって表、図、相互参照の採番方法を更新Go
  • VBAT または広電圧モードをバッテリ直接に更新および変更Go
  • 特長の VBAT 範囲を「2.3~3.63V」から「2.3~3.6V」に更新および変更Go
  • TX 電流を 150mA (54OFDM) から 223mA (54OFDM) に変更Go
  • Changed MODULE PIN DESCRIPTION for PIN NO. 47Go
  • Changed from Handling Ratings table to ESD Ratings tableGo
  • Added TX power/IBAT versus TX power level settings section Go
  • Deleted Reset Requirements table Go
  • Added graphs representing TX Power and IBAT vs TX Power Level Settings (1 DSSS, 6 OFDM, and 54 OFDM)Go
  • Changed Brownout and Blackout Conditions sectionGo
  • Added Electrical Characteristics Go
  • Changed VOH in Electrical Characteristics (3.3 V, 25°C) Go
  • Changed VOL in Electrical Characteristics (3.3 V, 25°C) Go
  • Changed the Low-level sink current VOH value from: 0.4 to: 0.6 in Section 8.8 Go
  • Deleted VOH and VOL from the pullup and pulldown current entries in Section 8.8 Go
  • Changed Figure 8-8 Go
  • Changed minimum clock period to 50 ns, maximum clock low period to 25 ns, and maximum clock high period to 25 ns in Host SPI Interface Timing Parameters Go
  • Changed minimum clock period to 50 ns, maximum clock low period to 25 ns, and maximum clock high period to 25 ns in Host SPI Interface Timing Parameters Go
  • Added clock frequency at VBAT = 3.3 V and VBAT ≤ 2.1 V in Host SPI Interface Timing Parameters Go
  • Added description for nHIB pin in Table 8-3 Go
  • Changed HOST_SPI_CLK from 24 MHz to 20 MHz in Table 8-3 Go
  • Added Section 8.13, Host UART Go
  • Added Section 9.1, Overview Go
  • Changed Figure 9-1 Go
  • Added Section 9.4, Wi-Fi Network Processor Subsystem Go
  • Added Table 9-1 Go
  • Changed in Section 9.5, Power Management Architecture Go
  • Added Section 9.6, Low-Power Operating Modes Go
  • Changed LPDS wakeup time from 10 ms to < 3 ms in Section 9.6.1, Low-Power Deep Sleep Go
  • Added Note 1 for Figure 10-1 Go
  • Changed the new Device and Documentation Support sectionGo
  • Added NOTE to Mechanical Drawing Go
  • Updated reel quantities in Section 13.2 Go
  • Changed Package Qty value for CC3100MODR11MAMOBR in Section 13.2.1 Go
  • Changed SPQ value for CC3100MODR11MAMOBR throughout Section 13.2.2 Go
  • Changed Pin1 Quadrant values in Section 13.2.2 Go