JAJSPO7C March   2015  – January 2023 DRV2700

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Converter and Control Loop
      2. 7.3.2 High-Voltage Amplifier
      3. 7.3.3 Fast Start-Up (Enable Pin)
      4. 7.3.4 Gain Control
      5. 7.3.5 Adjustable Boost Voltage
      6. 7.3.6 Adjustable Boost Current-Limit
      7. 7.3.7 Internal Charge Pump
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Boost + Amplifier Mode
      2. 7.4.2 Flyback Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 AC-Coupled DAC Input Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Piezo Load Selection
          2. 8.2.1.2.2  Programming The Boost Voltage
          3. 8.2.1.2.3  Inductor and Transformer Selection
          4. 8.2.1.2.4  Programing the Boost and Flyback Current-Limit
          5. 8.2.1.2.5  Boost Capacitor Selection
          6. 8.2.1.2.6  Pulldown FET and Resistors
          7. 8.2.1.2.7  Low-Voltage Operation
          8. 8.2.1.2.8  Current Consumption Calculation
          9. 8.2.1.2.9  Input Filter Considerations
          10. 8.2.1.2.10 Output Limiting Factors
          11. 8.2.1.2.11 Startup and Shutdown Sequencing
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Filtered AC Coupled Single-Ended PWM Input Application
      3. 8.2.3 DC-Coupled DAC Input Application
      4. 8.2.4 DC-Coupled Reference Input Application
      5. 8.2.5 Flyback Circuit
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost + Amplifier Configuration Layout Considerations
      2. 10.1.2 Flyback Configuration Layout Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGP|20
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TA = 25°C, VOUT(PP) = VOUT+ – VOUT– = 200 V, C(LOAD) = 47 nF, G(AMP) = 40 dB, L = 4.7 µH (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
|IIL|Digital-input low currentEN, GAIN0, GAIN1; VDD = 3.6 V, VI = 0 V1µA
|IIH|Digital-input high currentEN, GAIN0, GAIN1; VDD = 3.6 V, VI = VDD5µA
IL(sd)Shutdown currentVDD = 3.6 V, V(EN) = 0 V13µA
IQQuiescent currentVDD = 3.6 V, V(EN) = VDD, V(BST) = 105 V, no signal24mA
VDD = 3.6 V, V(EN) = VDD, V(BST) = 80 V, no signal13mA
VDD = 3.6 V, V(EN) = VDD, V(BST) = 55 V, no signal9mA
VDD = 3.6 V, V(EN) = VDD, V(BST) = 30 V, no signal5mA
VOSOffset voltageVDD = 3.6 V, V(EN) = 3.6 V25mV
CMVRCommon-mode voltageVDD = 3.6 V, V(EN) = 3.6 V0.2VDD – 0.4V
CMRRCommon-mode rejection ratioVDD = 3.6 V, V(EN) = 3.6 V100dB
PSRRPower-supply rejection ratioVDD = 3.6 V, V(EN) = 3.6 V60dB
RIInput impedanceAll gains, IN+, IN–100kΩ
G(AMP)Amplifier gainGAIN[1:0] = 0028.8dB
GAIN[1:0] = 0134.8
GAIN[1:0] = 1038.4
GAIN[1:0] = 1140.7
SRSlew rateGAIN[1:0] = 00, No Load150V/ms
GAIN[1:0] = 01, No Load300
GAIN[1:0] = 10, No Load450
GAIN[1:0] = 11, No Load600
BWAmplifier bandwidthGAIN[1:0] = 00, VOUT(PP) = 50 V, No Load20kHz
GAIN[1:0] = 01, VOUT(PP) = 100 V, No Load10
GAIN[1:0] = 10, VOUT(PP) = 150 V, No Load7.5
GAIN[1:0] = 11, VOUT(PP) = 200 V, No Load5
GBWGain-bandwidth productVDD = 3.6 V, V(EN) = 3.6 V550kHz
VnInput Voltage NoiseVDD = 3.6 V, V(EN) = 3.6 V6.5µV/√ Hz
THD+NTotal harmonic distortion plus noiseƒ = 300 Hz, VOUT(PP) = 200 V1%