SLVSCE5 Data sheet

SLVSCE5B November 2013 – July 2016 DRV3203E-Q1

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7 Detailed Description

7.1 Functional Block Diagram

7.2 Feature Description

7.2.1 Watchdog

A watchdog monitors the PRN signal and VCC supply level and generates a reset to the MCU through the RES pin if the status of PRN is not normal or VCC is lower than the specified threshold level. Detection of a special pattern on the PRN input during power up can disable the watchdog.

DRV3203E-Q1 Blk_Diag_Watchdog_SLVSC09.gif

Figure 8. Watchdog Block Diagram

7.2.2 Serial Port I/F

Setting device configuration and reading out diagnostic information is via SPI. SPI operates in slave mode. SPI uses four signals according to the timing chart of Figure 2.

Figure 9. Block Diagram of SPI

7.2.2.1 CS - Chip Select

The MCU uses CS to select the IC. CS is normally high, and communication is possible only when it is forced low. When CS falls, communication between the IC and the MCU starts. The transmitted data are latched and the DOUT output pin leaves high impedance. When CS rises, communication stops. The DOUT output pin goes into high impedance. The next falling edge starts another communication. There is a minimum waiting time between the two communications (t_wait). The pin has an internal pullup.

7.2.2.2 SCK - Synchronization Serial Clock

The MCU uses SCK to synchronize communication. SCK is normally low, and the valid clock-pulse number is 16. At each falling edge, the MCU writes a new bit on the DIN input, and this IC writes a new bit on the DOUT output pin. At each rising edge, this IC reads the new bit on DIN, and the MCU reads the new bit on DOUT. The maximum clock frequency is 4 MHz. The pin has an internal pulldown.

7.2.2.3 DIN - Serial Input Data

DIN receives 16-bit data. The order of received bits is from the MSB (first) to the LSB (last). The pin has an internal pulldown. Update of the internal register with the received bits occurs only if the number of clock pulses is 16 while CS is low.

7.2.2.4 DOUT - Serial Output Data

DOUT transmits 16-bit data. It is a three-state output, and it is in the high-impedance state when CS is high. The order of serial data-bit transmission is from the MSB (first) to the LSB (last).

7.2.3 Charge Pump

The charge-pump block generates a supply for the high-side and low-side pre-drivers to maintain the gate voltage on the external FETs. Use of an external storage capacitor (CCP) and bucket capacitors (C1, C2) supports pre-driver slope and switching-frequency requirements. R1 and R2 reduce switching current if required. The charge pump has voltage-supervisor functions such as over- and undervoltage, and selectable stop conditions for pre-drivers.

Figure 10. Charge-Pump Block Diagram

7.2.4 Pre-Driver

The pre-driver block provides three high-side pre-drivers and three low-side pre-drivers to drive external N-channel MOSFETs. The turnon side of the high-side pre-drivers supplies the large N-channel transistor current for quick charge, and PMOS supports output voltages up to PDCPV. The turnoff side of the high-side pre-drivers supplies the large N-channel transistor current for quick discharge. The low-side pre-drivers supply the large N-channel transistor current for charge and discharge. VCP12 (created by a charge pump) controls the output voltage of the low-side pre-driver to output less than 18 V. The pre-driver has a stop condition in some fault conditions (Fault Detection) and SPI set (Serial Port I/F).

DRV3203E-Q1 Blk_Diag_Pre-Driver_SLVSC09.gif

Figure 11. Pre-Driver Block Diagram

7.2.5 Phase Comparator

The three-channel comparator module monitors the external FETs by detecting the drain-source voltage across the high-side and low-side FETs. PHTM is the threshold level of the comparators usable for sensorless communication. Figure 12 shows an example of the threshold level.

Figure 12. Phase Comparator Block Diagram

7.2.6 Motor-Current Sense

The operational amplifier operates with an external resistor network for higher flexibility to adjust the current measurement to application requirements. The first-stage amplifier operates with the external resistor and the output voltage up to VB at ALFB. External resistors adjust the amplifier gain by 10 to 30 times. The second-stage amplifier is buffered to MCU at ALV. The current sense has a comparator for motor overcurrent (OVAD). ADTH is the overcurrent threshold level and is the value set by SPI. Figure 13 shows the curve of detection level. ALFB is divided by 2. Compare this value with ADTH. In recommended application, the zero-point adjustment is required as large error offset in initial condition.

Figure 13. Motor Current-Sense Block Diagram

7.2.7 Regulators

The regulator block offers 3.3-V LDOs. The VCC LDO regulates VB down to 3.3 V with an external PNP controlled by the regulator block. This 3.3-V LDO is supplied to MCU and other components.

The VDD regulator regulates VB down to 3.3 V with internal FET and controller. The 3.3-V LDO with the external PNP is protected against short to GND fault. Overvoltage and undervoltage events of both supplies are detected. The under voltage of the 3.3-V LDO with the external PNP is set by SPI.

Figure 14. VCC Block Diagram (External Driver)

Figure 15. VDD Block Diagram

7.2.8 VB Monitor

The VB monitoring system has two comparators for under- and overvoltage, and has pre-driver stop-controlling system. Overvoltage provides a selectable pre-driver stop condition (SPI control), while undervoltage must stop pre-driver operation under detection (no selectable). The system should return to normal operation automatically after undetected level.

Figure 16. VB Monitor Block Diagram

7.2.9 Thermal Shutdown

The device has temperature sensors that produce pre-driver stop condition if the chip temperature exceeds 175°C.

Figure 17. Thermal Shutdown Block Diagram

7.2.10 Oscillator

The oscillator block generates two 10-MHZ clock signals. OSC1 is the primary clock used for internal logic-synchronization and timing control. OSC2 is the secondary clock used to monitor the status of OSC1.

Figure 18. Oscillator Block Diagram

7.2.11 I/O

* V5INT is the internal power supply.

Figure 19. Input Buffer1 Block Diagram

Figure 20. Output Buffer1 Block Diagram

Figure 21. Output Buffer2 Block Diagram

Figure 22. Output Buffer3 Block Diagram

Table 1. Recommended Pin Termination

PIN NAME	DESCRIPTION	TERMINATION
TEST	Test mode input	OPEN

7.2.12 Fault Detection

Table 2. Fault Detection

ITEMS	SPI FLTFLG	Pre Driver⁽¹⁾	FAULT⁽²⁾	RES	Others
VB - Overvoltage	VBOV	Disable	L	H
VB - Undervoltage	VBUV	Disable	L	H
CP - Overvoltage	CPOV	Disable	L	H
CP - Undervoltage	CPUV	Disable	L	H
VCC - Overvoltage	VCCOV	Disable	L	H
VCC - Under Voltage	-	Disable⁽³⁾	H	L
VCC - Overcurrent	VCCOC	Disable	L	H
Motor - Overcurrent	MTOC	Disable	L	H
VDD - Overvoltage	VDDOV	Disable	L	H
VDD - Undervoltage	-	Disable⁽³⁾	H	L
Thermal shutdown	TSD	Disable	L	H
Watch Dog	-	-	H	L
Clock Monitor	-	-	H	L
SPI format error	-	-	H	H	SPI serial out error bit

(1) Pre-driver is disabled if the conditions occur and SDNEN register bits are 1.

(2) FAULT pin is asserted to low if the conditions occur and FLTEN register bits are 1.

(3) Pre-driver is disabled by VCC undervoltage and VDD undervoltage conditions regardless of SPI register setting.

7.3 Register Maps

Table 1. SPI Serial Input Format

MSB

D14

D13

D12

D11

D10

DIN

RW[1]

RW[0]

Addr[5]

Addr[4]

Addr[3]

Addr[2]

Addr[1]

Addr[0]

LSB

DIN

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2]

Data[1]

Data[0]

Table 2. SPI Serial Output Data Format

MSB

D14

D13

D12

D11

D10

DOUT

Frame fault

LSB

DOUT

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2]

Data[1]

Data[0]

SPI serial input and output format
RW[1:0]	:	01: write mode; 00: read mode
Addr[5:0]	:	Address of SPI access
Data[7:0]	:	Input data to write or output data to read
Frame fault	:	0: No error exists in the previous SPI frame.
	:	1: Error exists in the previous SPI frame.

Table 3. SPI Register Map

Register Name	Addr (Hex)	b7	b6	b5	b4	b3	b2	b1	b0	Reset (Hex)
Reserved	00	RSVD								00
CFGUNLK	01	RSVD				CFGUNLK				00
FLTCFG	02	FLGLATCH_EN	MTOCTH			RSVD	VCCUVTH	VBUVTH		00
Reserved	03	RSVD								00
FLTEN0	04	FE_MTOC	FE_VCCOC	FE_VCCOV	FE_VDDOV	FE_CPOV	FE_CPUV	FE_VBOV	FE_VBUV	FF
FLTEN1	05	RSVD							FE_TSD	01
SDNEN0	06	SE_MTOC	SE_VCCOC	SE_VCCOV	SE_VDDOV	SE_CPOV	SE_CPUV	SE_VBOV	SE_VBUV	FF
SDNEN1	07	RSVD							SE_TSD	01
FLTFLG0	08	MTOC	VCCOC	VCCOV	VDDOV	CPOV	CPUV	VBOV	VBUV	00
FLTFLG1	09	RSVD							TSD	00
CSCFG	0A	RSVD					CSOFFSET			00
PDCFG	0B	RSVD						DEADT		00
DIAG	0C	RSVD					VCCUVRST	WDTRST	CMRST	00
SPARE	0D	SPARE						SEL_COMP_HYS		00
Reserved	0E-3F	RSVD								00

7.3.1 Register Descriptions

Access type: R = Read and W = Write.
Reserved register: Read of reserved bits return 0 and write has no effect.

7.3.1.1 CFGUNLK (address 0x01): Configuration Unlock Register

Bit	Name	Type	Reset	Description
3:0	CFGUNLK	RW	0000	DRV3203E-Q1 SPI register map has lock and unlock mode, and it is in lock mode by default. MCU can write values of the following registers in unlock mode;
				● FLTCFG
				● FLTEN0 and FLTEN1
				● SDNEN0 and SDNEN1
				● CSCFG
				● PDCFG
				● WDCFG
				In lock mode, read returns the values, but writing the registers have no effect.
				Device enters unlock mode by writing 0x5, 0x8, 0x7 to CFGUNLK register in series. Device exits from unlock mode by writing 0x0.

7.3.1.2 FLTCFG (address 0x02): Fault Detection Configuration Register

Bit	Name	Type	Reset	Description
7	FLGLATCH_EN	RW	0	Fault-flag (FLTFLG*) latch enable
				0: Fault events do not latch fault-flag register bits.
				1: Latching of fault-flag register bits by the fault events occurs. The flag bits remain asserted until cleared.
6:4	MTOCTH	RW	000	Motor overcurrent detection threshold (ADTH) 000: 1.32 V 001: 1.65 V 010: 1.98 V 011: 2.31 V 100: 2.64 V Others: 1.32 V
3	RSVD	R	0	Reserved
2	VCCUVTH	RW	0	VCC undervoltage detection threshold 0: 2.2 V 1: 2.4 V
1:0	VBUVTH	RW	00	VB undervoltage detection threshold 00: 4 V 01: 4.5 V 10: 5 V 11: 5.5 V

7.3.1.3 FLTEN0 (address 0x04): FAULT Pin Enable Register 0

Bit	Name	Type	Reset	Description
7	FE_MTOC	RW	1	FAULT pin enable of FLTFLG0 register bits. 0: Assertion of the FAULT pin does not occur when the fault flag bit is 1 1: Assertion of the FAULT pin to low level occurs when the fault flag bit is 1. See Figure 23
6	FE_VCCOC	RW	1
5	FE_VCCOV	RW	1
4	FE_VDDOV	RW	1
3	FE_CPOV	RW	1
2	FE_CPUV	RW	1
1	FE_VBOV	RW	1
0	FE_VBUV	RW	1

7.3.1.4 FLTEN1 (address 0x05): FAULT Pin Enable Register 1

Bit	Name	Type	Reset	Description
7:1	RSVD	R	0000 000	Reserved
0	FE_TSD	RW	1	FAULT pin enable of TSD flag bit 0: Assertion of the FAULT pin does not occur when the fault flag bit is 1 1: Assertion of the FAULT pin to low level occurs when the TSD flag bit is 1. See Figure 23

Figure 23. FAULT Pin Enable Logic

7.3.1.5 SDNEN0 (address 0x06): Pre-Driver Shutdown Enable Register 0

Bit	Name	Type	Reset	Description
7	SE_MTOC	RW	1	Pre-driver shutdown enable of FLTFLG0 register bits 0: Disabling of the pre-driver outputs does not occur when the fault flag bit is 1. 1: Disabling of the pre-driver outputs occurs when the fault flag bit is 1. Both the high-side and low-side FETs turn off. See Figure 24.
6	SE_VCCOC	RW	1
5	SE_VCCOV	RW	1
4	SE_VDDOV	RW	1
3	SE_CPOV	RW	1
2	SE_CPUV	RW	1
1	SE_VBOV	RW	1
0	SE_VBUV	RW	1

7.3.1.6 SDNEN1 (address 0x07): Pre-Driver Shutdown Enable Register 1

Bit	Name	Type	Reset	Description
7:1	RSVD	R	0000 000	Reserved
0	SE_TSD	RW	1	Pre-driver shutdown enable of TSD flag bits 0: Disabling of the pre-driver outputs does not occur when the TSD flag bit is 1. 1: Disabling of the pre-driver outputs occurs when the TSD flag bit is 1. Both the high-side and low-side FETs turn off. See Figure 24.

Figure 24. Pre-Driver Shutdown Logic

7.3.1.7 FLTFLG0 (address 0x08): Fault Flag Register 0

Bit	Name	Type⁽¹⁾	Reset	Description
				Fault flag bits of the following conditions;⁽²⁾
7	MTOC	RW	0	MTOC: Motor overcurrent. (OVAD)
6	VCCOC	RW	0	VCCOC: VCC overcurrent
5	VCCOV	RW	0	VCCOV: VCC overvoltage
4	VDDOV	RW	0	VDDOV: VDD overvoltage
3	CPOV	RW	0	CPOV: Charge-pump overvoltage
2	CPUV	RW	0	CPUV: Charge-pump undervoltage
1	VBOV	RW	0	VBOV: VB overvoltage
0	VBUV	RW	0	VBUV: VB undervoltage
				If FLTCFG.FLGLATCH_EN = 1
				0:	Read = No fault condition exists since last cleared.
					Write = No effect
				1:	Read = Fault condition exists.
					Write = Clear the flag.
				If FLTCFG.FLGLATCH_EN = 0
				0:	Read = No fault condition
					Write = No effect
				1:	Read = Fault condition
					Write = No effect

(1) R: Read, W: Write

(2) Assertion of the fault flags may occur during power up.

7.3.1.8 FLGFLT1 (address 0x09): Fault Flag Register 1

Bit	Name	Type⁽¹⁾	Reset	Description
7:1	RSVD	R	0000 000	Reserved
0	VBUV	RW	1	Fault flag bit of thermal shutdown condition.⁽²⁾ If FLTCFG.FLGLATCH_EN = 1
				0:	Read = No fault condition exists since last cleared.
					Write = No effect
				1:	Read = Fault condition exists.
					Write = Clear the flag
				If FLTCFG.FLGLATCH_EN = 0
				0:	Read = No fault condition
					Write = No effect
				1:	Read = Fault condition
					Write = No effect

(1) R: Read, W: Write

(2) Assertion of the fault flags may occur during power up.

Figure 25. SPI Data-Out Timing Chart of Fault Flag Registers

1. Assertion of FAULT occurs if FLTEN = 1.

2. Disabling of pre-driveroccurs if SDNEN = 1.

Figure 26. FLGFLG and FLGLATCH_EN

7.3.1.9 CSCFG (address 0x0A): Current Sense Configuration Register

Bit	Name	Type⁽¹⁾	Reset	Description
7:3	RSVD	R	0000 0	Reserved
2:0	CSOFFSET	RW	000	Current-sense offset 000: 0.5 V 001: 1 V 010: 1.5 V Others: 0.5 V

(1) R: Read W: Write

7.3.1.10 PDCFG (address 0x0B): Pre-Driver Configuration Register

Bit	Name	Type⁽¹⁾	Reset	Description
7:2	RSVD	R	0000 00	Reserved
1:0	DEADT	RW	00	Dead time (= t_dead) 00: 2.1 µs 01: 1.6 µs 10: 1.1 µs 11: 0.6 µs The actual dead time has ±0.1-µs variation from the typical value.

(1) R: Read W: Write

7.3.1.11 DIAG (address 0x0C): Diagnosis Register

Bit	Name	Type	Reset	Description
7:3	RSVD	R	0000 0	Reserved
2	VCCUVRST	R	0	nRES reset source information
1	WDTRST	R	0	Bit 2 = VCCUVRST - VCC undervoltage
0	CMRST	R	0	Bit 1 = WDTRST - watchdog timer
				Bit 0 = CMRST - clock monitor
				0:	Read = Reset has not occurred.
					Write = No effect
				1:	Read = A corresponding reset source caused the last reset condition.
					Write = No effect
				Read access to this register clears the bits.

7.3.1.12 SPARE (address 0x0D): Spare Register

Bit	Name	Type⁽¹⁾	Reset	Description
7:2	SPARE	RW	0000 00	Spare registers for future use. Read and write have no effect.
1:0	SEL_COMP_HYS	RW	00	Select phase comparator hysteresis voltage. The following show the typical values. MM 00: 0 V MM 01: 25 mV MM 10: 50 mV MM 11: 100 mV

(1) R: Read W: Write