JAJSU38 データシート

JAJSU38 April 2024 DRV8215

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTE|16
- MPQF149D

サーマルパッド・メカニカル・データ

RTE|16
- QFND525B

発注情報

6.5 Electrical Characteristics

0 V ≤ V_VM ≤ 11 V and 1.65 V ≤ V_VCC ≤ 11 V, –40°C ≤ T_J ≤ 150°C (unless otherwise noted).
Typical values are at T_J = 27°C, V_VM = 5 V, V_VCC = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (VM, VCC)
I_VMQ	VM sleep mode current	nSLEEP = 0 V, V_VM = 5 V, V_VCC = 3.3 V, T_J = 27°C, OVP disabled		100	170	nA
I_{VMQ_OVP}	VM sleep mode current	nSLEEP = 0 V, V_VM = 5 V, V_VCC = 3.3 V, T_J = 27°C, OVP enabled		0.1	1	µA
I_VM	VM active mode current	nSLEEP = 3.3 V, EN/IN1 = 3.3 V, PH/IN2 = 0 V, V_VM = 5 V, V_VCC = 3.3 V		1.3	1.9	mA
I_VCCQ	VCC sleep mode current	nSLEEP = 0 V, V_VM = 5 V, V_VCC = 3.3 V, T_J = 27°C		1	3.0	nA
I_VCC	VCC active mode current	nSLEEP = 3.3 V, EN/IN1 = 3.3 V, PH/IN2 = 0 V, V_VM = 5 V, V_VCC = 3.3 V		1.5	2	mA
t_WAKE	Turnon time	nSLEEP = 1 to I²C ready			410	μs
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, SDA, SCL, nSLEEP)
V_IL	Input logic low voltage		0		0.4	V
V_IH	Input logic high voltage		1.45		5.5	V
V_HYS	Input hysteresis		49			mV
I_IL	Input logic low current	V_I = 0 V	-1		1	µA
I_IH	Input logic high current	V_I = 5 V	15		35	µA
R_PD	Input pulldown resistance, INx			200		kΩ
t_DEGLITCH	Input logic deglitch, INx			50		ns
TRI-LEVEL INPUTS (A1, A0)
V_THYS	Tri-level input logic low voltage		0		0.4	V
I_TIL	Tri-level input Hi-Z voltage		0.75		1.05	V
I_TIZ	Tri-level input logic high voltage		1.45		5.5	V
R_TPD	Tri-level pulldown resistance	to GND		90		kΩ
I_TPU	Tri-level pullup current	to VCC		10		µA
OPEN-DRAIN OUTPUTS (nFAULT, SDA)
V_OL	Output logic low voltage	I_OD = 5 mA			0.4	V
I_OZ	Output logic high current	V_OD = VCC	-1		1	µA
t_{PW_nFAULT}	nFAULT low pulse width	RC Count overflow, RC_REP = 11b	30	50	70	µs
C_B	SDA capacitive load for each bus line				400	pF
DRIVER OUTPUTS (OUTx)
R_{DS(ON)_HS}	High-side MOSFET on resistance	I_OUTx = 1 A; T_J = 25 °C		120	155	mΩ
R_{DS(ON)_HS}	High-side MOSFET on resistance	I_OUTx = 1 A; T_J = 125 °C		180	220	mΩ
R_{DS(ON)_HS}	High-side MOSFET on resistance	I_OUTx = 1 A; T_J = 150 °C		200	250	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 00Xb	I_OUTx = -1 A; T_J = 25 °C		120	145	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 00Xb	I_OUTx = -1 A; T_J = 125 °C		180	220	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 00Xb	I_OUTx = -1 A; T_J = 150 °C		200	250	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 01Xb	I_OUTx = -250 mA; T_J = 25 °C		440	530	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 01Xb	I_OUTx = -250 mA; T_J = 125 °C		660	800	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 01Xb	I_OUTx = -250 mA; T_J = 150 °C		750	900	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 11Xb	I_OUTx = -50 mA; T_J = 25 °C		2040	2450	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 11Xb	I_OUTx = -50 mA; T_J = 125 °C		3050	3650	mΩ
R_{DS(ON)_LS}	Low-side MOSFET on resistance, CS_GAIN_SEL = 11Xb	I_OUTx = -50 mA; T_J = 150 °C		3450	4150	mΩ
V_SD	Body diode forward voltage	I_OUTx = -1 A		0.9		V
t_RISE	Output rise time	V_OUTx rising from 10% to 90% of V_VM		100		ns
t_FALL	Output fall time	V_OUTx falling from 90% to 10% of V_VM		50		ns
t_PD	Input to output propagation delay	Input to OUTx		650		ns
t_DEAD	Output dead time			500		ns
CURRENT SENSE AND REGULATION (IPROPI, VREF)
V_{REF_INT}	Internal reference voltage	INT_VREF = 1b	480	500	520	mV
A_{IPROPI_H}	Current scaling factor	CS_GAIN_SEL = 000b, 350 mA to 2A		244		µA/A
A_{IPROPI_M}	Current scaling factor	CS_GAIN_SEL = 010b, 60 mA to 350 mA		1156		µA/A
A_{IPROPI_L}	Current scaling factor	CS_GAIN_SEL = 110b, 10 mA to 60 mA		5320		µA/A
A_{ERR_H}	Current mirror total error, CS_GAIN_SEL = 000b	I_OUT = 1 A, V_IPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ V_VM ≤ 11 V	-5		5	%
A_{ERR_H}	Current mirror total error, CS_GAIN_SEL = 000b	I_OUT = 1 A, V_IPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ V_VM ≤ 3.3 V	-5		5	%
A_{ERR_M}	Current mirror total error, CS_GAIN_SEL = 010b	I_OUT = 250 mA, V_IPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ V_VM ≤ 11 V	-5		5	%
A_{ERR_M}	Current mirror total error, CS_GAIN_SEL = 010b	I_OUT = 250 mA, V_IPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ V_VM ≤ 3.3 V	-5		5	%
A_{ERR_L}	Current mirror total error, CS_GAIN_SEL = 110b	I_OUT = 50 mA, V_IPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ V_VM ≤ 11 V	-6.5		6.5	%
A_{ERR_L}	Current mirror total error, CS_GAIN_SEL = 110b	I_OUT = 50 mA, V_IPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ V_VM ≤ 3.3 V	-6.5		6.5	%
t_OFF	Current regulation off time			20		µs
t_BLANK	Current sense blanking time	TBLANK = 0b		1.8		µs
t_BLANK	Current sense blanking time	TBLANK = 1b		1		µs
t_DEG	Current regulation and stall detection deglitch time	TDEG = 0b		2		µs
t_DEG	Current regulation and stall detection deglitch time	TDEG = 1b		1		µs
t_INRUSH	Inrush time blanking for stall detection		5		6716	ms
Voltage regulation
ΔV_LINE	Line regulation	4 V ≤ V_VM ≤ 11 V, V_VCC = 3.3 V, V_OUT = 3.3 V, I_OUT = 2 A		±1%
ΔV_LOAD	Load regulation	V_VM = 5 V, V_VCC = 3.3 V, V_OUT = 3.3 V, I_OUT = 100 mA to 2 A		±3%
PROTECTION CIRCUITS
V_{UVLO_VCC}	VCC supply undervoltage lockout (UVLO)	Supply rising			1.65	V
V_{UVLO_VCC}	VCC supply undervoltage lockout (UVLO)	Supply falling	1.30			V
V_{UVLO_HYS}	Supply UVLO hysteresis	Rising to falling threshold		120		mV
t_UVLO	Supply undervoltage deglitch time	V_VCC falling to OUTx disabled		10		µs
V_{OVP_TH}	Overvoltage protection threshold	V_OUT - V_VM		200		mV
t_{OVP_ON}	Overvoltage protection turn-on time			13		µs
t_{OVP_OFF}	Overvoltage protection turn-off time			250		µs
I_OCP	Overcurrent protection trip point, CS_GAIN_SEL = 000b		4			A
I_OCP	Overcurrent protection trip point, CS_GAIN_SEL = 010b		0.8			A
I_OCP	Overcurrent protection trip point, CS_GAIN_SEL = 110b		0.16			A
t_OCP	Overcurrent protection deglitch time			2		µs
t_RETRY	Retry time			1.7		ms
T_TSD	Thermal shutdown temperature		157	175	193	°C
T_HYS	Thermal shutdown hysteresis			18		°C