JAJSBL7F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1 System Management Bus (SMBus) and Configuration Registers

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ to VDD to enable SMBus Reader MODE and allow access to the configuration registers.

The DS80PCI402 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS reader address inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS80PCI402 has a 7-bit reader address. The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the AD[3:0] inputs. Below are the 16 addresses.

Table 8-6 Device reader Address Bytes
AD[3:0] SETTINGSADDRESS BYTES (HEX)7-BIT reader ADDRESS (HEX)
0000B058
0001B259
0010B45A
0011B65B
0100B85C
0101BA5D
0110BC5E
0111BE5F
1000C060
1001C261
1010C462
1011C663
1100C864
1101CA65
1110CC66
1111CE67

The SDA/SCL pins are 3.3 V tolerant, but are not 5 V tolerant. An external pullup resistor is required on the SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.