JAJSSV1B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Low-Speed Output Signal Control

The FPC202 has four general-purpose outputs per port which can be used to drive the low-speed inputs to the module. The host controller can change the state of these outputs for each port individually, for all ports connected to a given FPC202 device simultaneously, or for all ports in the system simultaneously.

There are two configuration registers for these outputs. One register configures the enable state of the S0_OUT_A, S0_OUT_B, S1_OUT_A, and S1_OUT_B pins for every port, and by default the S0_OUT_A, S0_OUT_B, S1_OUT_A, and S1_OUT_B pins are disabled (tri-stated). The second register controls the output value for all S0_OUT_A, S0_OUT_B, S1_OUT_A, and S1_OUT_B pins, where S0_OUT_A/S1_OUT_A have default values of '1' and S0_OUT_B/S1_OUT_B have default values of '0'. The output values should be configured before the outputs are enabled. If a default value is desired during boot-up before these pins are enabled, a 10-kΩ pull-up or pull-down resistor is recommended (note that SFP and QSFP modules have internal pull-up and pull-downs on certain inputs). Note that if the VDD1 rail does not have power and there is an externally powered pull-up resistor connected to an output pin, the output pin will be pulled low until VDD1 is supplied.

An example signal connection is provided below. S0_OUT_A, S0_OUT_B, S1_OUT_A, and S1_OUT_B are not restricted to this port pin assignment, and they can be used to drive any 3.3-V signal required for the application, provided the IOH and IOL limits are met.

Table 7-1 Example Connections for Low-Speed FPC202 Outputs to SFP/QSFP ports
PIN NAMEEXAMPLE CONNECTIONCOMMENT
SFPQSFP
S0_OUT_ATx_DisableResetL
S0_OUT_BRS0LPModeAlternatively, RS0 and RS1 be driven to the same level by using just one output.
S1_OUT_ARS1
S1_OUT_BGeneral-purpose output, available for any purpose