JAJSB30I August   2010  – April 2018 LM25119

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-Up Regulator
      2. 8.3.2  UVLO
      3. 8.3.3  Enable 2
      4. 8.3.4  Oscillator and Sync Capability
      5. 8.3.5  Error Amplifiers and PWM Comparators
      6. 8.3.6  Ramp Generator
      7. 8.3.7  Current Limit
      8. 8.3.8  Hiccup Mode Current Limiting
      9. 8.3.9  Soft Start
      10. 8.3.10 HO and LO Output Drivers
      11. 8.3.11 Maximum Duty Cycle
      12. 8.3.12 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Diode Emulation
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Miscellaneous Functions
      2. 9.1.2 Interleaved Two-Phase Operation
      3. 9.1.3 Interleaved 4-Phase Operation
    2. 9.2 Typical Applications
      1. 9.2.1 Dual-output Design Example
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 External Components
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Timing Resistor
          2. 9.2.1.2.2  Output Inductor
          3. 9.2.1.2.3  Current Sense Resistor
          4. 9.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 9.2.1.2.5  Output Capacitors
          6. 9.2.1.2.6  Input Capacitors
          7. 9.2.1.2.7  VCC Capacitor
          8. 9.2.1.2.8  Bootstrap Capacitor
          9. 9.2.1.2.9  Soft Start Capacitor
          10. 9.2.1.2.10 Restart Capacitor
          11. 9.2.1.2.11 Output Voltage Divider
          12. 9.2.1.2.12 UVLO Divider
          13. 9.2.1.2.13 MOSFET Selection
          14. 9.2.1.2.14 MOSFET Snubber
          15. 9.2.1.2.15 Error Amplifier Compensation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Two-Phase Design Example
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Switching Jitter Root Causes and Solutions
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 コミュニティ・リソース
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Hiccup Mode Current Limiting

To further protect the regulator during prolonged current limit conditions, an internal counter counts the PWM clock cycles during which cycle-by-cycle current limiting occurs. When the counter detects 256 consecutive cycles of current limiting, the regulator enters a low power dissipation hiccup mode with the HO and LO outputs disabled. The restart timer pin, RES, and an external capacitor configure the hiccup mode current limiting. A capacitor on the RES pin (CRES) determines the time the controller remains in low power standby mode before automatically restarting. A 10-µA current source charges the RES pin capacitor to the 1.25-V threshold which restarts the overloaded channel. The two regulator channels operate independently. One channel may operate normally while the other is in the hiccup mode overload protection. The hiccup mode commences when either channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting. If that occurs, the overloaded channel turns off and remains off for the duration of the RES pin timer.

The hiccup mode current-limiting function can be disabled. The RES configuration is latched during initial power up when UVLO is above 1.25 V and VCC1 and VCC2 are above their UV thresholds, determining hiccup or non-hiccup current limiting. If the RES pin is tied to VCC at initial power on, hiccup current limit is disabled.