JAJSOX6 October   2023 LM74930-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Charge Pump
      2. 7.3.2  Dual Gate Control (DGATE, HGATE)
        1. 7.3.2.1 Load Disconnect Switch Control (HGATE, OUT)
        2. 7.3.2.2 Reverse Battery Protection (A, C, DGATE)
      3. 7.3.3  Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
      4. 7.3.4  Overcurrent Protection with Circuit Breaker (ILIM, TMR)
      5. 7.3.5  Overcurrent Protection With Latch-Off
      6. 7.3.6  Short-Circuit Protection (ISCP)
        1. 7.3.6.1 Device Wake-Up With Output Short-Circuit Condition
      7. 7.3.7  Analog Current Monitor Output (IMON)
      8. 7.3.8  Overvoltage and Undervoltage Protection (OV, UVLO, OVCLAMP)
      9. 7.3.9  Disabling Reverse Current Blocking Functionality (MODE)
      10. 7.3.10 Device Functional Modes
        1. 7.3.10.1 Low Quiescent Current Shutdown Mode (EN)
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 200-V Unsuppressed Load Dump Protection Application
      1. 8.2.1 Design Requirements for 200-V Unsuppressed Load Dump Protection
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  VS Capacitance, Resistor R1 and Zener Clamp (DZ)
        2. 8.2.2.2  Charge Pump Capacitance VCAP
        3. 8.2.2.3  Input and Output Capacitance
        4. 8.2.2.4  Overvoltage and Undervoltage Protection Component Selection
        5. 8.2.2.5  Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        6. 8.2.2.6  Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        7. 8.2.2.7  Selection of Current Sense Resistor, RSNS
        8. 8.2.2.8  Hold-Up Capacitance
        9. 8.2.2.9  MOSFET Q1 Selection
        10. 8.2.2.10 MOSFET Q2 Selection
        11. 8.2.2.11 Input TVS Selection
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Transient Protection
      2. 8.4.2 TVS Selection for 12-V Battery Systems
      3. 8.4.3 TVS Selection for 24-V Battery Systems
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = 12 V, V(AC) = 20 mV, C(VCAP) = 0.1 µF, V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
V(VS) Operating input voltage 4 65 V
V(VS_PORR) VS POR threshold, rising 2.4 2.6 2.9 V
V(VS_PORF) VS POR threshold, falling 2.2 2.1 2.7 V
I(SHDN) Shutdown current, I(GND) V(EN) = 0 V 2.5 5 µA
I(Q) Total system quiescent current, I(GND) V(EN) = 2 V 665 780 µA
I(REV) I(A)  leakage current during reverse polarity, 0 V ≤ V(A) ≤ – 65 V –100 –35 µA
I(OUT) leakage current during reverse polarity –1 –0.3 µA
ENABLE
V(ENR) Enable threshold voltage for low Iq shutdown, rising 0.8 1.05 V
V(ENF) Enable falling threshold voltage for low Iq shutdown 0.41 0.7 V
I(EN/UVLO) 0 V ≤ V(EN) ≤ 65 V 55 200 nA
MODE
V(MODEF) MODE falling threshold voltage  0.41 0.7 V
V(MODER) MODE threshold, rising 0.8 1.05 V
I(MODE) MODE input leakage current 100 160 nA
UNDERVOLTAGE LOCKOUT COMPARATOR
V(UVLOR) UVLO threshold voltage, rising 0.585 0.6 0.63 V
V(UVLOF) UVLO threshold voltage, falling 0.533 0.55 0.573 V
I(UVLO) 0 V ≤ V(UVLO) ≤ 5 V 50 200 nA
OVERVOLTAGE PROTECTION AND BATTERY SENSING INPUT
R(SW) Battery sensing disconnect switch resistance 10 19.5 46 Ω
V(OVR) Overvoltage threshold input, rising 0.585 0.6 0.63 V
V(OVF) Overvoltage threshold input, falling 0.533 0.55 0.573 V
I(OV) OV Input leakage current 0 V ≤ V(OV) ≤ 5 V 50 200 nA
V(OVCLAMPR) OVCLAMP threshold input, rising 0.57 0.59 0.61 V
V(OVCLAMPF) OVCLAMP threshold input, falling 0.435 0.45 0.475 V
I(OVCLAMP) OVCLAMP Input leakage current 0 V ≤ V(OV) ≤ 5 V 53 200 nA
CURRENT SENSE AMPLIFIER
V(OFFSET) Input referred offset RSET = 50Ω RIMON = 5 kΩ (corresponds to VSNS = 6 mV to 30 mV) –2.1 2.1 mV
V(GE_SET) VSNS to VIMON scaling RSET = 50Ω RIMON = 5 kΩ (corresponds to VSNS = 6 mV to 30 mV) 82 90 97
V(SNS_TH) OCP comparator rising threshold 1.08 1.22V 1.32 V
OCP comparator falling threshold 1.02 1.15 1.25 V
ISCP SCP input bias current 9.5 11 12 µA
V(HV_SCP) HV SCP comparator threshold VCS– > 3V 17.4 20 22 mV
V(HV_SCP) HV SCP comparator threshold RISCP = 1kΩ 31 mV
IMON Accuracy Current monitor output accuracy VSENSE = 20 mV, RIMON = 5kΩ –12.5 12.5 %
V(LV_SCP) LV SCP comparator threshold VCS– < 3V 16.5 20 24 mV
FAULT
R(FLT) FLT pull-down resistance 10 22 60 Ω
I_FLT FLT input leakage current –100 400 nA
DELAY TIMER 
I(TMR_SRC_OCP) TMR source current during overcurrent 65 85 97 µA
I(TMR_SRC_OVCLAMP) TMR source current during overvoltage clamp 4.5 5.5 6.6 µA
I(TMR_SRC_FLT) TMR source current  1.94 2.97 3.5 µA
I(TMR_SNK) TMR sink  current 2 2.7 3.15 µA
V(TMR_OC) Voltage at TMR pin for ILIM shut off 1.1 1.2 1.4 V
V(TMR_FLT) Voltage at TMR pin for FLT trigger 1.04 1.1 1.2 V
V(TMR_LOW) Voltage at TMR pin for auto-retry counter falling threshold 0.1 0.2 0.3 V
N(A_R_Count) Number of auto-retry cycles 32
CHARGE PUMP
I(CAP) Charge pump source current  V(CAP) – V(A) = 7 V, 6 V ≤ V(S) ≤ 65 V  1.3 2.7 mA
VCAP – VS Charge pump turn-on voltage 11 12.2 13.2 V
Charge pump turn-off voltage 11.9 13.2 14.1 V
V(CAP UVLO) Charge pump UVLO voltage threshold, rising 5.4 6.6 7.9 V
Charge pump UVLO voltage threshold, falling 4.4 5.5 6.6 V
IDEAL DIODE
V(A_PORR) V(A) POR threshold, rising 2.2 2.45 2.7 V
V(A_PORF) V(A) POR threshold, falling 2 2.25 2.45 V
V(AC_REG) Regulated forward V(A)–V(C) threshold 3.6 10.4 13.7 mV
V(AC_REV) V(A)–V(C) threshold for fast reverse current blocking –16 –10.5 –5 mV
V(AC_FWD) V(A)–V(C) threshold for reverse to forward transition 150 177 200 mV
V(DGATE) – V(A) Gate drive voltage 4 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 9.2 11.5 14 V
I(DGATE) Peak gate source current V(A) – V(C) = 300 mV, V(DGATE) – V(A) = 1 V 18.5 mA
Peak gate sink current V(A) – V(C) = –12 mV, V(DGATE) – V(A) = 11 V 2670 mA
Regulation sink current V(A) – V(C) = 0 V, V(DGATE) – V(A) = 11 V,  5 13.5 µA
I(C) Cathode leakage Current V(A) = –14 V, V(C) = 12 V 9.3 32 µA
HIGH SIDE CONTROLLER 
V(HGATE) – V(OUT) Gate drive voltage 4 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 10 11.1 14.5 V
I(HGATE) Source current 39 55 75 µA
Sink current 128 180 mA