JAJSOX6 October   2023 LM74930-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Charge Pump
      2. 7.3.2  Dual Gate Control (DGATE, HGATE)
        1. 7.3.2.1 Load Disconnect Switch Control (HGATE, OUT)
        2. 7.3.2.2 Reverse Battery Protection (A, C, DGATE)
      3. 7.3.3  Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
      4. 7.3.4  Overcurrent Protection with Circuit Breaker (ILIM, TMR)
      5. 7.3.5  Overcurrent Protection With Latch-Off
      6. 7.3.6  Short-Circuit Protection (ISCP)
        1. 7.3.6.1 Device Wake-Up With Output Short-Circuit Condition
      7. 7.3.7  Analog Current Monitor Output (IMON)
      8. 7.3.8  Overvoltage and Undervoltage Protection (OV, UVLO, OVCLAMP)
      9. 7.3.9  Disabling Reverse Current Blocking Functionality (MODE)
      10. 7.3.10 Device Functional Modes
        1. 7.3.10.1 Low Quiescent Current Shutdown Mode (EN)
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 200-V Unsuppressed Load Dump Protection Application
      1. 8.2.1 Design Requirements for 200-V Unsuppressed Load Dump Protection
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  VS Capacitance, Resistor R1 and Zener Clamp (DZ)
        2. 8.2.2.2  Charge Pump Capacitance VCAP
        3. 8.2.2.3  Input and Output Capacitance
        4. 8.2.2.4  Overvoltage and Undervoltage Protection Component Selection
        5. 8.2.2.5  Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        6. 8.2.2.6  Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        7. 8.2.2.7  Selection of Current Sense Resistor, RSNS
        8. 8.2.2.8  Hold-Up Capacitance
        9. 8.2.2.9  MOSFET Q1 Selection
        10. 8.2.2.10 MOSFET Q2 Selection
        11. 8.2.2.11 Input TVS Selection
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Transient Protection
      2. 8.4.2 TVS Selection for 12-V Battery Systems
      3. 8.4.3 TVS Selection for 24-V Battery Systems
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(C) = V(OUT) = V(VS) = 12V, V(AC) = 20 mV, C(VCAP) = 0.1 µF, V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDGATE_OFF(dly) DGATE turn-off delay during reverse voltage detection V(A) – V(C) = +30 mV to –100 mV to V(DGATE–A) < 1 V, C(DGATE–A) = 10 nF 0.5 0.95 µs
tDGATE_ON(dly) DGATE turn-on delay during forward voltage detection V(A) – V(C) = –20 mV to +700 mV to V(DGATE-A) > 5 V, C(DGATE-A) = 10 nF 2 3.8 µs
tEN(dly)_DGATE DGATE turn-on delay during enable EN↑ to V(DGATE-A) > 5 V, C(DGATE-A) = 10 nF 180 270 µs
tUVLO_OFF(deg)_HGATE HGATE turn-off de-glitch during UVLO UVLO↓ to HGATE ↓ 5 7 µs
tUVLO_ON(deg)_HGATE HGATE turn-on de-glitch during UVLO UVLO ↑ to HGATE ↑ 8.5 µs
tOVP_OFF(deg)_HGATE HGATE turn-off de-glitch during OV OV ↑ to HGATE ↓ 4 7 µs
tOVP_ON(deg)_HGATE HGATE turn-on de-glitch during OV OV ↓ to HGATE ↑ 9 µs
tSCP_DLY Short circuit protection turn-off delay (VISCP – VCS–) = 0 mv to 100 mV HGATE↓, CGS = 4.7 nF
 		 3.5 5.5 µs
tSCP_DLY_START Short circuit protection turn-off delay at start-up V(VS) = 12 V, V(CS–) = 0 V 4 4.6 µs
tOCP_TMR_DLY Overcurrent protection turn-off delay (VCS+ – VCS–)↑  HGATE↓, CTMR = 50 pF
 		 35 µs
tOCP_TMR_DLY Overcurrent protection turn-off delay (VCS+ – VCS–)↑  HGATE↓, CTMR = 10 nF 190 µs
tAUTO_RETRY_DLY Over current / Short circuit protection auto retry delay (VCS+ – VCS–)↑  HGATE↑, CTMR = 50 pF
 		 1.5 ms
tAUTO_RETRY_DLY Overvoltage clamp timer delay (VCS+ – VCS–)↑  HGATE↑, CTMR = 10 nF 230 ms
tFLT_ASSERT Fault assert delay (VCS+ – VCS–)↑  FLT↓, CTMR = 50 pF 35 µs
tFLT_ASSERT_UV/OV Fault assert delay during UVLO or OV 3 µs
tFLT_DE-ASSERT Fault de-assert delay 4 µs
tMODE_ENTRY No RCB mode entry delay 5 µs
tMODE_ENTRY No RCB to RCB mode entry delay 6 µs