JAJSDO2C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics: VS = 3 V

at VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈ 25°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL(1)
AC PERFORMANCE
SSBWSmall-signal bandwidthVOUT = 20 mVPP, G = 6 (peaking < 4 dB)7086MHzC
VOUT = 20 mVPP, G = 10, RF = 1.6 kΩ50C
VOUT = 20 mVPP, G = 100, RF = 16.9 kΩ3C
GBPGain-bandwidth productVOUT = 20 mVPP, G = 100240300MHzC
LSBWLarge-signal bandwidthVOUT = 2 VPP, G = 645MHzC
Bandwidth for 0.1-dB flatnessVOUT = 200 mVPP, G = 69MHzC
SRSlew rateFrom LSBW(2)250350V/µsC
Overshoot, undershootVOUT = 1-V step, G = 6, input tR = 6 ns2%4%C
tR, tFRise, fall timeVOUT = 1-V step, G = 6, input tR = 6 ns6.37nsC
Settling time to 0.1%VOUT = 1-V step, G = 6, input tR = 6 ns30nsC
Settling time to 0.01%VOUT = 1-V step, G = 6, input tR = 6 ns40nsC
HD2Second-order harmonic distortionf = 100 kHz, VO = 2 VPP, G = 6 (see Figure 9-1)–108dBcC
HD3Third-order harmonic distortionf = 100 kHz, VO = 2 VPP, G = 6 (see Figure 9-1)–125dBcC
Input voltage noisef > 1 kHz1.8nV/√ HzC
Voltage noise 1/f corner frequency100HzC
Input current noisef > 100 kHz1.0pA/√ HzC
Current noise 1/f corner frequency7kHzC
Overdrive recovery timeG = 6, 2 × output overdrive, DC-coupled50nsC
Closed-loop output impedancef = 1 MHz, G = 60.3ΩC
DC PERFORMANCE
AOLOpen-loop voltage gainVO = ±1 V, RL = 2 kΩ110125dBA
Input-referred offset voltageTA ≈ 25°C–125±15125µVA
TA = 0°C to 70°C–165±15200B
TA = –40°C to +85°C–230±15220B
TA = –40°C to +125°C–230±15285B
Input offset voltage drift(5)TA = –40°C to +125°C (4)–1.6±0.41.6µV/°CB
Input bias current(3)TA ≈ 25°C.71.52.8µAA
TA = 0°C to 70°C.21.53.5B
TA = –40°C to +85°C.21.53.7B
TA = –40°C to +125°C.21.54.4B
Input bias current drift(5)TA = –40°C to +125°C4.57.817nA/°CB
Input offset currentTA ≈ 25°C–70±2070nAA
TA = 0°C to 70°C–83±2093B
TA = –40°C to +85°C–105±20100B
TA = –40°C to +125°C–105±13120B
Input offset current drift(5)TA = –40°C to +125°C–500±20500pA/°CB
INPUT
Common-mode input range, lowTA ≈ 25°C, CMRR > 92 dBVS– – 0.2VS– – 0VA
TA = –40°C to +125°C, CMRR > 92 dBVS– – 0B
Common-mode input range, highTA ≈ 25°C, CMRR > 92 dBVS+ – 1.3VS+ – 1.2VA
TA = –40°C to +125°C, CMRR > 92 dBVS+ – 1.3B
CMRRCommon-mode rejection ratio95105dBA
Input impedance common-mode55 || 1.1MΩ || pFC
Input impedance differential mode30 || 1.3kΩ || pFC
OUTPUT
VOLOutput voltage, lowTA ≈ 25°C, G = 6VS– + 0.05VS– + 0.1VA
TA = –40°C to +125°C, G = 6VS– + 0.1VS– + 0.2B
VOHOutput voltage, highTA ≈ 25°C, G = 6VS+ – 0.1VS+ – 0.05VA
TA = –40°C to +125°C, G = 6VS+ – 0.2VS+ – 0.1B
Maximum current into a resistive loadTA ≈ 25°C, ±0.77 V into 26.7 Ω, VIO < 2 mV±28±30mAA
Linear current into a resistive loadTA ≈ 25°C, ±0.88 V into 37 Ω, AOL > 70 dB±23±25mAA
TA = –40°C to +125°C, ±0.76 V into 37 Ω,
AOL > 70 dB		±20±23B
DC output impedanceG = 60.02ΩC
POWER SUPPLY
Specified operating voltage2.755.4VB
Quiescent operating currentTA ≈ 25°C(6)8909301025µAA
TA = –40°C to +125°C6809301350B
dIq/dTQuiescent current temperature coefficientTA = –40°C to +125°C2.22.73.2µA/°CB
+PSRRPositive power-supply rejection ratio95110dBA
–PSRRNegative power-supply rejection ratio90105dBA
POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)
Enable voltage thresholdSpecified on above VS– + 1.5 V1.5VA
Disable voltage thresholdSpecified off  below VS– + 0.55 V0.55VA
Disable pin bias currentPD = VS– to VS+–502050nAA
Power-down quiescent currentPD = 0.55 V0.11µAA
Turn-on time delayTime from PD = high to VOUT = 90% of final value3.5µsC
Turn-off time delayTime from PD = low to VOUT = 10% of original value100nsC
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √ 2) × 2π × f–3dB where this f–3dB is the typical measured 2-VPP bandwidth at gains of 6 V/V.
(3) Current is considered positive out of the pin.
(4) Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the full temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.
(5) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.
(6) The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.