JAJSQ80C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
STANDARD IO (TEST1, TEST2, ADDR, SCL, SDA, IRQ, REFCLK, EN, GPIO[4:1])
VILLow-level control signal input voltage0.3 ×
VCCIO
V
VIHHigh-level control signal input voltage0.7 ×
VCCIO
V
VOHHigh-level output voltageIOH = –2 mA1.3V
VOLLow-level output voltageIOL = 2 mA0.4V
IIHHigh-level input currentAny input terminal±5μA
IILLow-level input current
IOZHigh-impedance output currentAny output terminal±10μA
IOSShort-circuit output currentAny output driving GND short±2mA
ICCAVCCA device active currentVCCA = 1.2 V (2)70126mA
ICCVCC device active currentVCCA = 1.2 V (2)4352mA
ICCIOVCCIO and VPLL device active currentVCCIO = 1.8 V, VPLL = 1.8 V (2)3232mA
ISUSPEND_CCAVCCA device suspend currentAll data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 19.8mA
ISUSPEND_CCVCC device suspend currentAll data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 19mA
ISUSPEND_CCIOVCCIO and VPLL device suspend currentAll data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 11.16mA
IEN_CCAVCCA shutdown currentEN = 00.95mA
IEN_CCVCC shutdown currentEN = 02mA
IEN_CCIOVCCIO and VPLL shutdown currentEN = 00.038mA
RENEN control input resistor150
ADDR, EN, SCL, SDA, DBP/N[3:0], DAP/N[3:1], DBCP/N, DACP/N
ILEAKInput failsafe leakage currentVCC = 0; VCCIO = 0 V. Input pulled up to VCCIO max. DSI inputs pulled up to 1.3 V–4040µA
MIPI DSI INTERFACE
VIH-LPLP receiver input high thresholdSee Figure 7-5880mV
VIL-LPLP receiver input low threshold550mV
VOH-LPLP transmitter high-level output voltage11001300mV
VOL-LPLP transmitter low-level output voltage–5050mV
VIHCDLP Logic 1 contention threshold450mV
VILCDLP Logic 0 contention threshold200mV
|VID|HS differential input voltage70270mV
|VIDT|HS differential input voltage threshold50mV
VIL-ULPSLP receiver input low threshold; ultra-low power state (ULPS)300mV
VCM-HSHS common mode voltage; steady-state70330mV
ΔVCM-HSHS common mode peak-to-peak variation including symbol delta and interference100mV
VIH-HSHS single-ended input high voltageSee Figure 7-5460mV
VIL-HSHS single-ended input low voltage–40mV
VTERM-ENHS termination enable; single-ended input voltage (both Dp AND Dn apply to enable)Termination is switched simultaneous for Dn and Dp450mV
RDIFF-HSHS mode differential input impedance80125Ω
DisplayPort MAIN LINK
VTX_DC_CMOutput common mode voltage02V
VTX_AC_CM_HBR_RBRTX AC common mode voltage for HBR and RBR.20mVRMS
VTX_AC_CM_HBR2TX AC common mode voltage for HBR230mVRMS
VTX_DIFFPP_LVL0Differential peak-to-peak output voltage level 0Based on default state of V0_P0_VOD register300400460mV
VTX_DIFFPP_LVL1Differential peak-to-peak output voltage level 1Based on default state of V1_P0_VOD register450600690mV
VTX_DIFFPP_LVL2Differential peak-to-peak output voltage level 2Based on default state of V2_P0_VOD register600800920mV
VTX_DIFFPP_LVL3Differential peak-to-peak output voltage level 3Based on default state of V3_P0_VOD register. Level 3 is not enabled by default600800920mV
VTX_PRE_RATIO_0Pre-emphasis level 0000dB
VTX_PRE_RATIO_1Pre-emphasis level 12.83.54.2dB
VTX_PRE_RATIO_2Pre-emphasis level 24.86.07.2dB
VTX_PRE_RATIO_3Pre-emphasis level 3Level 3 is not enabled by default4.86.07.2dB
VTX_PRE_POST2_RATIO_0Post-cursor2 level 0000dB
VTX_PRE_POST2_RATIO_1Post-cursor2 level 1–1.1–0.9–0.7dB
VTX_PRE_POST2_RATIO_2Post-cursor2 level 2–2.3–1.9–1.5dB
VTX_PRE_POST2_RATIO_3Post-cursor2 level 3Level 3 is not enabled by default–3.7–3.1–2.5dB
ITX_SHORTTX short circuit current limit50mA
RTX_DIFFDifferential impedance80100120Ω
CAC_COUPLINGAC coupling capacitor75200nF
DisplayPort HPD
VHPD_PLUGHot plug detection thresholdMeasured at 51-kΩ series resistor.2.2V
VHPD_UNPLUGHot unplug detection thresholdMeasured at 51-kΩ series resistor.0.8V
RHPDPDHPD internal pulldown resistor516069
DisplayPort AUX INTERFACE
VAUX_DIFF_PP_TXPeak-to-peak differential voltage at transmit pinsVAUX_DIFF_PP = 2 × |VAUXP – VAUXN|0.181.38V
VAUX_DIFF_PP_RXPeak-to-peak differential voltage at receive pinsVAUX_DIFF_PP = 2 × |VAUXP – VAUXN|0.181.36V
RAUX_TERMAUX channel termination DC resistance100Ω
VAUX_DC_CMAUX channel DC common mode voltage01.2V
VAUX_TURN_CMAUX channel turnaround common-mode voltage0.3V
IAUX_SHORTAUX Channel short circuit current limit90mA
CAUXAUX AC-coupling capacitor75200nF
All typical values are at VCC = 1.2 V, VCCA = 1.2 V, VCCIO = 1.8 V, and VPLL = 1.8 V, and TA = 25°C
Maximum condition: WQXGA 60 fps Dual-Link 2xDP at HBR2, PLL enabled; typical condition: WUXGA 60 fps 1xDP at HBR2, PLL enabled