SLLSEA8A January   2012  – March 2016 SN65LVCP114

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VCC 2.5 V ±5%)
    6. 7.6 Electrical Characteristics (VCC 3.3 V ±5%)
    7. 7.7 Electrical Characteristics (VCC 3.3 V ±5%, 2.5 V ±5%)
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
    2. 8.2 Equivalent Input and Output Schematic Diagrams
    3. 8.3 Functional Definitions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Down
      2. 9.3.2  Lane Enable
      3. 9.3.3  Gain and Equalization
      4. 9.3.4  VOD
      5. 9.3.5  AGC
      6. 9.3.6  GPIO or I2C Configuration
      7. 9.3.7  Fast Switching
      8. 9.3.8  Power-Down Input Stages
      9. 9.3.9  Disable Output Lanes
      10. 9.3.10 Polarity Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Loopback
      3. 9.4.3 Diagnostic
    5. 9.5 Programming
      1. 9.5.1 Two-Wire Serial Interface and Control Logic
    6. 9.6 Register Maps
      1. 9.6.1 SN65LVCP114 Register Mapping Information
        1. 9.6.1.1  Register 0x00
        2. 9.6.1.2  Register 0x01
        3. 9.6.1.3  Register 0x02
        4. 9.6.1.4  Register 0x03
        5. 9.6.1.5  Register 0x04
        6. 9.6.1.6  Register 0x06
        7. 9.6.1.7  Register 0x07
        8. 9.6.1.8  Register 0x08
        9. 9.6.1.9  Register 0x0A
        10. 9.6.1.10 Register 0x0B
        11. 9.6.1.11 Register 0x0C
        12. 9.6.1.12 Register 0x0D
        13. 9.6.1.13 Register 0x0F
        14. 9.6.1.14 Register 0x10
        15. 9.6.1.15 Register 0x11
        16. 9.6.1.16 Register 0x12
        17. 9.6.1.17 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Transmit-Side Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Receive-Side Typical Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documenation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN65LVCP114 device has enough equalization to be placed on the receiver side and compensate traces up to 24 inches. The SN65LVCP114 device can be placed on transmitter side and still have an open eye after a trace of 24 inches.

10.2 Typical Applications

10.2.1 Transmit-Side Typical Application

SN65LVCP114 Tx_side_app_llsea8.gif Figure 34. Transmit-Side Typical Application

10.2.1.1 Design Requirements

Table 17 lists the design parameters of the SN65LVCP114.

Table 17. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VCC 3.3 V
VOD 600 mV
EQ 13.9 dB
GAIN 0.5 (–6 dB)
Trace length 16 inches

10.2.1.2 Detailed Design Procedure

  • Determine the loss profile between transmitter and receiver.
  • Based upon loss profile and signal swing, determine the optimal equalization settings.
  • Select appropriate voltage output swing.
  • If required select correct differential pair polarity.
  • To set voltage logic levels on configuration pins, use a 5-kΩ pullup for high level, tie pin to GND for low level, and place a 5-kΩ pullup and 5-kΩ pulldown for HiZ.

10.2.1.3 Application Curves

SN65LVCP114 app_curve_Input_to_SN65LVCP114_SLLSEA8.gif Figure 35. Input to SN65LVCP114
SN65LVCP114 app_curve_Output_to_SN65LVCP114_After_Trace_SLLSEA8.gif Figure 36. Output to SN65LVCP114 After Trace

10.2.2 Receive-Side Typical Application

SN65LVCP114 Rx_side_app_llsea8.gif Figure 37. Receive-Side Typical Application

10.2.2.1 Design Requirements

Table 18 lists the design parameters of the SN65LVCP114.

Table 18. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VCC 3.3 V
VOD 600 mV
EQ 13.9 dB
Gain 1 (0 dB)
Trace lenght 24 inches

10.2.2.2 Detailed Design Procedure

  • Determine the loss profile between transmitter and receiver.
  • Based upon the loss profile and signal swing, determine the optimal equalization settings.
  • Select appropriate voltage output swing.
  • If required, select the correct differential pair polarity.
  • To set voltage logic levels on configuration pins, use a 5-kΩ pullup for high level, tie pin to GND for low level, and place a 5-kΩ pullup and 5-kΩ pulldown for HiZ.

10.2.2.3 Application Curves

SN65LVCP114 app_curve_Input_to_SN65LVCP114_1_SLLSEA8.gif Figure 38. Input to SN65LVCP114
SN65LVCP114 app_curve_Output_to_SN65LVCP114_After_Trace_1_SLLSEA8.gif Figure 39. Output to SN65LVCP114 After Trace