JAJSSA4E August   2003  – April 2024 SN74AHC595-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements, VCC = 3.3 V ± 0.3 V
    6. 5.6 Timing Requirements, VCC = 5 V ± 0.5 V
    7. 5.7 Timing Diagrams
    8. 5.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    9. 5.9 Switching Characteristics, VCC = 5 V ± 0.5 V
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Power Supply Recommendations
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Document Support (Analog)
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • BQB|16
  • PW|16
サーマルパッド・メカニカル・データ
発注情報

7.3 Device Functional Modes

Table 7-1 Function Table
INPUTS FUNCTION
SER SRCLK SRCLR RCLK OE
X X X X H Outputs QA–QH are disabled.
X X X X L Outputs QA–QH are enabled.
X X L X X Shift register is cleared.
L ↑ H X X First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H ↑ H X X First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X X X ↑ X Shift-register data is stored into the storage register.