JAJSU11 March   2024 SN74LV3T99-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
  9. 8 Feature Description
    1. 8.1 Balanced CMOS 3-State Outputs
    2. 8.2 LVxT Enhanced Input Voltage
    3. 8.3 Clamp Diode Structure
  10. 9 Device Functional Modes
    1. 9.1 Logic Configurations
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power Considerations
        2. 10.2.1.2 Input Considerations
        3. 10.2.1.3 Output Considerations
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2. 13.2 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

10.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.

The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74LV3T99-Q1 plus the maximum static supply current, ICC, listed in the Electrical Characteristics and any transient current required for switching. The logic device can only source as much current as is provided by the positive supply source. Ensure the maximum total current through VCC listed in the Absolute Maximum Ratings is not exceeded.

The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74LV3T99-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only sink as much current as can be sunk into its ground connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not exceeded.

The SN74LV3T99-Q1 can drive a load with a total capacitance less than or equal to 50pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50pF.

The SN74LV3T99-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices.

CAUTION:

The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device.