JAJSDN3F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Parameter Measurement Information

GUID-D9BCC105-3CDB-44E8-AC44-CCBF196F1100-low.gif Figure 6-1 TMDS Main Link Test Circuit
GUID-825811C3-058A-4350-B577-87FE22DCE48F-low.gif Figure 6-2 Input or Output Timing Measurements
GUID-5B6910F2-E32F-439F-AE5B-73B0CC5FBFF1-low.gif Figure 6-3 Output Differential Waveform
GUID-EC9E5E9C-EA18-4CBD-8A08-6A642A2B3715-low.gif Figure 6-4 Output Differential Waveform with De-Emphasis
GUID-06577A4D-6832-46BC-881C-AAD341663B03-low.gif
The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling capacitor, connector and another 1-8” of FR4. Trace width – 4 mils. 100Ω differential impedance.
All Jitter is measured at a BER of 109
Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP
AVCC = 3.3V
RT = 50Ω
The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.
Figure 6-5 HDMI Output Jitter Measurement
GUID-77CB1A31-B4D8-4CD4-B66F-FA9FDFDC8D2F-low.gif Figure 6-6 Output Eye Mask at TTP4_EQ for HDMI 2.0
TMDS Data Rate (Gbps) H (Tbit) V (mV)
3.4 < DR < 3.712 0.6 335
3.712 < DR < 5.94 –0.0332Rbit2 + 0.2312 Rbit + 0.1998 –19.66Rbit2 + 106.74Rbit + 209.58
5.94 ≤ DR ≤ 6.0 0.4 150
GUID-20220712-SS0I-KRQZ-SQ7W-SHQXW0WLDX0F-low.svg Figure 6-7 HPD Test Circuit
GUID-8C9C5743-2A40-440D-BDF4-74B5136F9E05-low.gif Figure 6-8 HPD Timing Diagram No. 1
GUID-FD40BF43-1CBC-45CD-B1B8-EADE9D45262C-low.gif Figure 6-9 HPD Logic Disconnect Timeout
GUID-C7068894-A815-4502-A5B6-BA46669CCD57-low.gif Figure 6-10 Start and Stop Condition Timing
GUID-169BEEDD-45A8-43C2-975F-6A0CF469A27E-low.gif Figure 6-11 SCL and SDA Timing
GUID-20888608-82BC-4016-B65D-08B477AD31DE-low.gif Figure 6-12 DDC Propagation Delay – Source to Sink
GUID-007C7F85-BE7C-41C2-A7D5-65D7AB58F9E6-low.gif Figure 6-13 DDC Propagation Delay – Sink to Source
GUID-34A632E0-85F4-4020-8A99-852A97BB7A7E-low.gif Figure 6-14 VID(DC) and VID(EYE)