8.3.1 Maximum Constant Sink Current

The maximum output current of each channel (I_O(LCmax)) is programmed by a single resistor (R_IREF) that is placed between the IREF and GND pins. The current value can be calculated by Equation 1:

Equation 1.

where

I_O(LCmax) is the highest current for each output. Each output sinks I_O(LCmax) current when it is turned on with the maximum global brightness control (BC) data. Each output sink current can be reduced by lowering the global brightness control value. R_IREF must be between 1.32 kΩ and 66 kΩ to hold I_O(LCmax) between 50 mA (typical) and 1 mA (typical). Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved by setting I_O(LCmax) to 1 mA or higher and then using the global brightness control to lower the output current.

Figure 14 and Table 1 show the characteristics of the constant-current sink versus the external resistor, R_IREF.

8.3.2 Global Brightness Control (BC) Function

The TLC59291 has the ability to adjust the output current of all constant current outputs simultaneously. This function is called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) can be set with a 7-bit word. The global BC adjusts all output currents in 128 steps from 0% to 100%. where 100% corresponds to the maximum output current set by R_IREF. Equation 2 calculates the actual output current. BC data can be set via the serial interface.

Equation 2.

where

Table 2 shows the BC data versus the constant-current ratio against I_O(LCmax).

8.3.3 Thermal Shutdown (TSD) and Thermal Error Flag (TEF)

The thermal shutdown (TSD) function turns off all constant-current outputs when the junction temperature (T_J) exceeds the threshold (T_TEF = 165°C, typical) and sets all LOD data bit to ‘1’. When the junction temperature drops below (T_TEF – T_HYST), the output control starts. The TEF is remains ‘1’ until LAT is input even if low temperature. Figure 6 shows a timing diagram and Table 3 shows a truth table for TEF.

8.3.4 Pre-Thermal Warning (PTW)

The PTW function indicates that the IC junction temperature is high. The PTW is set and all LSD data bit are set to “1” while the IC junction temperature exceeds the temperature threshold (T_PTW = 138 °C, typical). Then OUTn are not forced off. When the PTW is set, the IC temperature should be reduced by lowering the power dissipated in the driver to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be accomplished by lowering the values of the BC data. When the IC junction temperature decreases below the temperature of T_PTW, PTW is reset. Figure 6 shows a timing diagram and Table 3 shows a truth table for PTW.

8.3.5 Current Reference Terminal – IREF Terminal - Short Flag (ISF)

The ISF function indicates that IREF terminal is short to GND with low impedance. When IREF is set, all OLD data bit is set to “1”. Then all outputs (OUTn) are forced off and remain off until the short is removed. Table 3 shows the truth table for ISF.

8.3.6 Noise Reduction

Large surge currents may flow through the IC and the board on which the device is mounted if all 16 outputs turn on simultaneously when BLANK goes low or on-off data changes at LAT rising edge with BLANK low. These large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC59291 turns the outputs on in 2ns series delay for each output to provide a circuit soft-start feature.

8.4.1 Blank Mode Selection (BLKMS)

The device has two configuration for BLANK pin, which is decided by BIT[9] in FC register. When BLANK mode = 1, the device is in ENABLE mode, BLANK pin is worked as OUTPUT enable pin: when BLANK=Low, all constant current outputs are controlled by the on/off control data in the data latch; when BLANK=High, all OUTx are forced off.

When BLANK mode = 0, the device is in SOUT mode, BLANK pin is worked as SOUT select pin; when BLANK= Low, SOUT is connected to the bit7 of the 16-bit shift register, worked as 8 channel device; when BLANK= High, SOUT is connected to the bit15 of the 16-bit shift register, worked as 16ch device. If device is already in ENABLE mode and we want to switch to SOUT mode, the new FC data with BIT[9]=0 must be input. Then it enter SOUT mode.

If device is already in SOUT mode and the user wants to switch to ENABLE mode. First make sure BLANK pin is high, SOUT is connected with bit15 of common shift register. Then input the new FC data with BIT[9] = 1. The device enters ENABLE mode

When the IC is powered on, SOUT mode is selected as default value. Refer to table 7 for detail.

8.4.2 Power-Save Mode

In this mode, the device dissipation current becomes 30 µA (typical). When “PSMODE” bit is ‘1’, the power save mode is enabled. Then if LAT rising edge is input to write all ‘0’ data into the output on-off data latch or to write any data into the control data latch when the on-off data latch are all ‘0’, TLC5929 goes into the power save mode. When SCLK rising edge is input, the device returns to normal operation. The power-save mode timing is shown in Figure 7.

8.4.3 LED Open Detection (LOD)

LOD detects the fault caused by LED open circuit or a short from OUTn to ground by comparing the OUTn voltage to the LOD detection threshold voltage level (V_LOD = 0.3 V typical). If the OUTn voltage is lower than V_LOD, that output LOD bit is set to '1' to indicate an open LED. Otherwise, the LOD bit is set to '0'. LOD data are only valid for outputs programmed to be on. LOD data for outputs programmed to be off are always '0' (Table 11).

The LOD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set to ‘01b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LOD data are stored to SID holder at the end timing of IDM working time.

The stored LOD data can be read out through the common shift register as Status Information Data (SID) from SOUT pin. LOD/LSD data are not valid until 0.5 µs after the falling edge of BLANK.

8.4.4 LED Short Detection (LSD)

LSD data detects the fault caused by a shorted LED by comparing the OUTn voltage to the LSD detection If the OUTn voltage is higher than the programmed voltage, that output LSD bit is set to '1' to indicate a shorted LED. Otherwise, the LSD bit is set to'0'. LSD data are only valid for outputs programmed to be on. LSD data for outputs programmed to be off are always '0' (Table 4).

The LSD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set to ‘10b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LSD data are stored to SID holder at the end timing of IDM working time. The stored LSD data can be read out through the common shift register as Status Information Data (SID) from SOUT pin. LOD/LSD data are not stabled until 0.5 µs after the falling edge of BLANK. Therefore, BLANK must be low for at least that time.

The LSD need to be executed after propagation delay, “t_d4” or more from the device operation resumed from the power save mode because LOD does not work during the power save mode.

8.4.5 Invisible Detection Mode (IDM)

Invisible Detection Mode (IDM) is the mode which can detect LOD and LSD when output on-off data is set to off state. When “IDMCUR” bit in the control data latch are set any data except “00b”, OUTn start to sink the current set by the “IDMCUR” bit at BLANK falling edge and OUTn stop to sink the current at BLANK rising signal or the time set by “IDMTIM” has passed. When OUTn is stopped, the selected SID data by “SIDLD” bit are latched to into SID holder.

When IDM mode is enabled, OLD is always set to disable. When “IDMCUR” bit in the control data latch is set “00b”, OUTn doesn’t start to sink the current set. Figure 29 shows LOD/LSD/OLD/IDM circuit. Figure 8 shows IDM operation timing and Table 5 shows a truth table for LOD/LSD/OLD.

IDM can only be working when FC[9] = 1.

8.4.6 Output Leakage Detection (OLD)

Output leak detection (OLD) detects a fault caused by OUTn is short to GND with high resistance by comparing the OUTn voltage to the LSD detection threshold voltage when output on-off data is set to off state. Also OLD can detect the short between adjacent pins. Small current is sourced from OUTn turned off to LED to detect LED leaking when “SIDLD” bit are ‘11b’ and BLANK is low. OLD operation is disabled when SIDLD bit are set any data except “11b” and then the sourced current is stopped. Also OLD is disabled when Invisible Detection Mode (IDM) is enabled. If the OUTn voltage is lower than the programmed LSD threshold voltage, that output OLD bit is set to '1' to indicate a leaking LED. Otherwise, the OLD bit is set to '0'. OLD result is valid for outputs programmed to off only. The OLD data is latched into SID holder when BLANK goes high. OLD data for outputs not programmed to off are always '0'. The OLD need to be executed after propagation delay, “td4” or more from the device operation resumed from the power save mode because OLD does not work during the power save mode.

Figure 29. LOD/LSD/OLD/IDM Circuit

8.4.7 Status Information Data (SID)

The status information data (SID) contains the status of the LED Open Detection (LOD), LED Short Detection (LSD), Output Leakage Detection (OLD), Pre-Thermal Warning (PTW), Thermal Shutdown (TSD) and Thermal Error Flag (TEF) and Current Reference Terminal – IREF Terminal - Short Flag (ISF). The loaded SID data can be selected by “SIDLD” bits in the control data latch. When the MSB of the common shift register is set to '0', the selected SID overwrites lower 16-bit data in the common shift register data at the rising edge of LAT after the data in the common shift register are copied to the output on-off data latch. If the common shift register MSB is '1', the selected SID does not overwrite the 16-bit data in the common shift register

After being copied into the common shift register, new SID data are not available until new data are written into the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID without changing the on-off control data, reprogram the common shift register with the same data currently programmed into the on-off data latch. When LAT goes high, the output on-off data is not changed, but new SID data are loaded into the common shift register. LOD, LSD, OLD, PTW, TEF, ISF are shifted out of SOUT with each rising edge of SCLK. The SID need to be read out after t_d4 or more from the device operation resumed from the power save mode.

The SID reading must be delayed for a duration of t_D4 or more after the device resumes operation from the power-save mode because SID does not indicate correct data during the power-save mode. The SID load configuration and SID read timing are shown in Figure 10 and Figure 30, respectively.

Figure 30. SID Load Configuration

8.5.1 Register and Data Latch Configuration

The TLC59291 has one common shift register and two control data latch. The common shift register is 16-bits in length and two control data latch is 16-bits length. When SCLK is '0' at LAT rising edge, the 16-bits common shift register are copied into the output on-off data latch. Also when SCLK is '1' at LAT rising edge the 16-bits data are copied into the control data latch. Figure 31 shows the common shift register and two control data latches configuration.

Figure 31. Common Shift Register and Control Data Latches Configuration

8.5.1.2 Output On/Off Data Latch

The output on/off data latch is 16 bits long and sets the on or off status for each constant-current output.

When FC[9] = 1 and BLANK is high, all outputs are forced off. But then the data in the latch are not changed. In other case, the corresponding output is turned on if the data in the output on-off data latch are '1' and remains off if the data are '0'.

When the IC is initially powered on, the data in the data latch is set to all “0”.

The output on/off data latch configuration is shown in Figure 32 and the data bit assignment is shown in Table 6.

Figure 32. Output On/Off Data Latch Configuration

Table 6. On/Off Control Data Latch Bit Assignment

BIT NUMBER	BIT NAME	CONTROLLED CHANNEL
0	OUTON0	OUT0
1	OUTON1	OUT1
2	OUTON2	OUT2
∙ ∙ ∙	∙ ∙ ∙	∙ ∙ ∙
13	OUTON13	OUT13
14	OUTON14	OUT14
15	OUTON15	OUT15

Figure 33. Output On/Off Data Latch

15	14	13	12	11	10	9	8
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. Output On/Off Data Latch

Bit	Field	Type	Reset	Description
[15]	OUTON15	R/W	00	When IC is powered up, these all data are set to “0” 0 = output OFF (default) 1 = output ON
[14]	OUTON14	R/W	00
[13]	OUTON13	R/W	00
[12]	OUTON12	R/W	00
[11]	OUTON11	R/W	00
[10]	OUTON10	R/W	00
[9]	OUTON9	R/W	00
[8]	OUTON8	R/W	00
[7]	OUTON7	R/W	00
[6]	OUTON6	R/W	00
[5]	OUTON5	R/W	00
[4]	OUTON4	R/W	00
[3]	OUTON3	R/W	00
[2]	OUTON2	R/W	00
[1]	OUTON1	R/W	00
[0]	OUTON0	R/W	00

8.5.1.3 Control Data Latch

The control data latch is 16-bit in length and contains the Global Brightness Control (BC) Function data, Status Information Data (SID) load select data, Blank Mode Selection (BLKMS) data, the current value for Invisible Detection Mode (IDM), IDM working time, and Power-Save Mode enable control data.

When the device is powered up, the data in this data latch are set to the default values shown in Table 8.

The function control data latch configuration is shown in Figure 34.

Figure 34. Function Control Data Latch Configuration

Figure 35. Control Data Latch

15	14	13	12	11	10	9	8
1	0	0	0	0	1	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
7	6	5	4	3	2	1	0
0	1	1	1	1	1	1	1
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Control Data Latch

Bit	Field	Type	Reset	Description
[15]	PSMODE	R/W	1b	Power save mode enable (Default value = ‘1b’) The data selects power save mode enable or disable. When the mode is enabled, the device goes into power save mode if all data in the on/off data latch are “0”. Table 15 shows the power save mode truth table. Figure 7 shows the power save mode operation timing.
[14:13]	IDMTIM	R/W	00b	IDM working time select (Default value = ‘00b’) The data selects the time of output current sink at OUTn for IDM to detect LED open detection (LOD) or LSD without visible lighting. Table 15 shows the work time truth table.Figure 9 shows the IDM operation timing.
[12:11]	IDMCUR	R/W	00b	IDM current select (Default value = ‘00b’) The data selects the sink current at OUTn for IDM to detect LED open detection (LOD) or LSD without visible lighting. Table 14 shows the current value truth table. Figure 9 shows the IDM operation timing.
[10]	LSDVLT	R/W	1b	LSD detection voltage select. (Default value = ‘1b’) These two bits select the detection threshold voltage for the LED short detection (LSD). Table 12 shows the detect voltage truth table.
[9]	BLKMS	R/W	0b	BLANK Mode Select (Default value = ‘0b’) The data selects the working mode for BLANK pin. Table 11 shows the truth table.
[8:7]	SIDLD	R/W	00b	SID load control (Default value = ‘00b’) The data selects the SID data loaded to the common register when LAT pulse is input for on-off data writing. Table 10 shows the selected data truth table.
[6:0]	BCALL	R/W	1111111b	Global brightness control (Default value = ‘1111111b’) The 7-bit data controls the current of all output with 128 steps between 0~100% of the maximum current value set by a external resistor. Table 13 shows the current value truth table.