SLVSA96A September   2015  – March 2016 TLC59291

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Maximum Constant Sink Current
      2. 8.3.2 Global Brightness Control (BC) Function
      3. 8.3.3 Thermal Shutdown (TSD) and Thermal Error Flag (TEF)
      4. 8.3.4 Pre-Thermal Warning (PTW)
      5. 8.3.5 Current Reference Terminal - IREF Terminal - Short Flag (ISF)
      6. 8.3.6 Noise Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Blank Mode Selection (BLKMS)
      2. 8.4.2 Power-Save Mode
      3. 8.4.3 LED Open Detection (LOD)
      4. 8.4.4 LED Short Detection (LSD)
      5. 8.4.5 Invisible Detection Mode (IDM)
      6. 8.4.6 Output Leakage Detection (OLD)
      7. 8.4.7 Status Information Data (SID)
    5. 8.5 Register Maps
      1. 8.5.1 Register and Data Latch Configuration
        1. 8.5.1.1 Common Shift Register
        2. 8.5.1.2 Output On/Off Data Latch
        3. 8.5.1.3 Control Data Latch
        4. 8.5.1.4 Output On/Off Data Write Timing and Output Control
        5. 8.5.1.5 Function Control Data Writing
        6. 8.5.1.6 Function Control (FC) Data
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
(Top View)
TLC59291 po_RGE_slvsa96.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BLANK 18 I BLANK PIN, has two configures:
When FC9(BLANK Mode) = 0, Blank pin worked as SOUT select pin:
  1. When BLANK = Low, SOUT is connected to the bit 7 of the 16-bit shift register, worked as 8ch device;
  2. When BLANK = High, SOUT is connected to the bit 15 of the 16-bit shift register, worked as 16ch device;

When FC9(BLANK Mode) = 1, Blank pin worked as OUTPUT enable pin;
  1. When BLANK = Low, all constant current outputs are controlled by the on/off control data in the data latch.
  2. When BLANK = High, all OUTx are forced off
GND 22 — Ground
IREF 20 I/O Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-current output. When this terminal is directly connected to GND, all outputs are forced off. The external resistor should be placed close to the device and must be in the range of 1.32 kΩ to 66 kΩ.
LAT 1 I Data latch.
The rising edge of LAT latches the data from the common shift register into the output on/off data latch. At the same time, the data in the common shift register are replaced with SID, which is selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID) section for more details.
OUT0 2 O Constant-current sink outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output.
OUT1 3 O
OUT2 4 O
OUT3 5 O
OUT4 6 O
OUT5 7 O
OUT6 8 O
OUT7 9 O
OUT8 10 O
OUT9 11 O
OUT10 12 O
OUT11 13 O
OUT12 14 O
OUT13 15 O
OUT14 16 O
OUT15 17 O
SCLK 24 I Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit shift register with the SCKI rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of the common shift register appear on SOUT.
SIN 23 I Serial data input for the 16-bit common shift register.
When SIN is high, a '1' is written to the LSB of the common shift register at the rising edge of SCLK.
SOUT 19 O Serial data output of the 16-bit common shift register.
When FC9(BLANK Mode) = 0 and BLANK = LOW;
SOUT is connected to the bit 7 of the 16-bit shift register. Data are clocked out at the SCLK rising edge.
In other case:
SOUT is connected to the bit 15 of the 16-bit shift register. Data are clocked out at the SCLK rising edge.
VCC 21 — Power-supply voltage