JAJSF52 April   2018 TPA3126D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      TPA3126とTPA3116のアイドル電流
      2.      アプリケーションの簡略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gain Setting and Master and Slave
      2. 8.3.2  Input Impedance
      3. 8.3.3  Startup and Shutdown Operation
      4. 8.3.4  PLIMIT Operation
      5. 8.3.5  GVDD Supply
      6. 8.3.6  BSPx and BSNx Capacitors
      7. 8.3.7  Differential Inputs
      8. 8.3.8  Device Protection System
      9. 8.3.9  DC Detect Protection
      10. 8.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 8.3.11 Thermal Protection
      12. 8.3.12 Device Modulation Scheme
        1. 8.3.12.1 BD Modulation
      13. 8.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 8.3.14 Ferrite Bead Filter Considerations
      15. 8.3.15 When to Use an Output Filter for EMI Suppression
      16. 8.3.16 AM Avoidance EMI Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mono PBTL Mode
      2. 8.4.2 Mono BTL Mode (Single Channel Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Select the PWM Frequency
          2. 9.1.1.2.2 Select the Amplifier Gain and Master/Slave Mode
          3. 9.1.1.2.3 Select Input Capacitance
          4. 9.1.1.2.4 Select Decoupling Capacitors
          5. 9.1.1.2.5 Select Bootstrap Capacitors
        3. 9.1.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Heat Sink Used on the EVM
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 関連資料
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Gain Setting and Master and Slave

The gain of the TPA3126D2 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four states set the GAIN in Master mode with gains of 20, 26, 32, and 36 dB respectively, while the next four states set the GAIN in Slave mode with gains of 20, 26, 32, and 36 dB respectively. The gain setting is latched during power-up and cannot be changed while the device is powered on. Table 1 lists the recommended resistor values for different state settings.

Table 1. Gain and Master/Slave

MASTER / SLAVE MODE GAIN R1 (to GND)(1) R2 (to GVDD)(1) INPUT IMPEDANCE
Master 20 dB 5.6 kΩ OPEN 60 kΩ
Master 26 dB 20 kΩ 100 kΩ 30 kΩ
Master 32 dB 39 kΩ 100 kΩ 15 kΩ
Master 36 dB 47 kΩ 75 kΩ 9 kΩ
Slave 20 dB 51 kΩ 51 kΩ 60 kΩ
Slave 26 dB 75 kΩ 47 kΩ 30 kΩ
Slave 32 dB 100 kΩ 39 kΩ 15 kΩ
Slave 36 dB 100 kΩ 16 kΩ 9 kΩ
(1) Resistor tolerance should be 5% or better.
TPA3126D2 GAIN_SETTING_MASTER_SLAVE_los708.gifFigure 25. Gain, Master/Slave

In Master mode, the SYNC terminal is an output, while in Slave mode, the SYNC terminal is an input for a clock. TTL logic levels with compliance to GVDD.