JAJSF52
April 2018
TPA3126D2
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
TPA3126とTPA3116のアイドル電流
アプリケーションの簡略回路図
4
改訂履歴
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
DC Electrical Characteristics
7.6
AC Electrical Characteristics
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Gain Setting and Master and Slave
8.3.2
Input Impedance
8.3.3
Startup and Shutdown Operation
8.3.4
PLIMIT Operation
8.3.5
GVDD Supply
8.3.6
BSPx and BSNx Capacitors
8.3.7
Differential Inputs
8.3.8
Device Protection System
8.3.9
DC Detect Protection
8.3.10
Short-Circuit Protection and Automatic Recovery Feature
8.3.11
Thermal Protection
8.3.12
Device Modulation Scheme
8.3.12.1
BD Modulation
8.3.13
Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
8.3.14
Ferrite Bead Filter Considerations
8.3.15
When to Use an Output Filter for EMI Suppression
8.3.16
AM Avoidance EMI Reduction
8.4
Device Functional Modes
8.4.1
Mono PBTL Mode
8.4.2
Mono BTL Mode (Single Channel Mode)
9
Application and Implementation
9.1
Application Information
9.1.1
Typical Application
9.1.1.1
Design Requirements
9.1.1.2
Detailed Design Procedure
9.1.1.2.1
Select the PWM Frequency
9.1.1.2.2
Select the Amplifier Gain and Master/Slave Mode
9.1.1.2.3
Select Input Capacitance
9.1.1.2.4
Select Decoupling Capacitors
9.1.1.2.5
Select Bootstrap Capacitors
9.1.1.3
Application Curves
10
Power Supply Recommendations
10.1
Power Supply Mode
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
Heat Sink Used on the EVM
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
開発サポート
12.2
ドキュメントの更新通知を受け取る方法
12.3
関連資料
12.4
コミュニティ・リソース
12.5
商標
12.6
静電気放電に関する注意事項
12.7
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DAD|32
MPDS503A
サーマルパッド・メカニカル・データ
DAD|32
PPTD344A
発注情報
jajsf52_oa
jajsf52_pm
9.1.1.3
Application Curves
Figure 35.
Total Harmonic Distortion + Noise (PBTL) vs Output Power
Figure 36.
Maximum Output Power (PBTL) vs Supply Voltage