JAJSED7B January   2018  – August 2018 TPA3220

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (PBTL)
    8. 7.8 Typical Characteristics, BTL Configuration, AD-mode
    9. 7.9 Typical Characteristics, PBTL Configuration, AD-mode
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Internal LDO
        1. 9.3.1.1 Input Configuration, Gain Setting And Master / Slave Operation
      2. 9.3.2 Gain Setting And Master / Slave Operation
      3. 9.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 9.3.4 Oscillator
      5. 9.3.5 Input Impedance
      6. 9.3.6 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Powering Up
        1. 9.4.1.1 Startup Ramp Time
      2. 9.4.2 Powering Down
        1. 9.4.2.1 Power Down Ramp Time
      3. 9.4.3 Device Reset
      4. 9.4.4 Device Soft Mute
      5. 9.4.5 Device Protection System
        1. 9.4.5.1 Overload and Short Circuit Current Protection
        2. 9.4.5.2 Signal Clipping and Pulse Injector
        3. 9.4.5.3 DC Speaker Protection
        4. 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.5.5 Overtemperature Protection OTW and OTE
        6. 9.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 9.4.5.7 Fault Handling
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 BST capacitors
          4. 10.2.1.2.4 PCB Material Recommendation
      2. 10.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 10.2.2.1 Design Requirements
      3. 10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 10.2.3.1 Design Requirements
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 AVDD and GVDD Supplies
      3. 11.1.3 PVDD Supply
      4. 11.1.4 BST Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DDW|44
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, TC (Case temperature) = 75 °C, fS = 480 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
AVDD Voltage regulator. Only used as reference node when supplied by internal LDO. Voltage regulator bypassed for VDD = 5 V. VDD = 30 V 5 V
IVDD VDD supply current. LDO mode (VDD > 7 V) Operating, no audio signal 25 mA
Reset mode 118 µA
VDD supply current. LDO bypass mode (VDD = 5 V) Operating, no audio signal 150
Reset mode 50
IAVDD Gate-supply current. LDO bypass mode (VDD = 5 V) Operating, no audio signal 10 mA
Reset mode 1
IGVDD Gate-supply current. LDO bypass mode (VDD = 5 V), AD-mode modulation 50% duty cycle 16
Reset mode 50 µA
Gate-supply current. LDO bypass mode (VDD = 5 V), HEAD-mode modulation HEAD-mode modulation 16 mA
Reset mode 50 µA
IPVDD Total PVDD idle current, AD-mode modulation, BTL 50% duty cycle with recommended output filter 17 mA
50% duty cycle with recommended output filter, TC = 25 ºC 17
Reset mode, No switching 1
Total PVDD idle current, HEAD-mode modulation, BTL HEAD-mode modulation with recommended output filter 12
HEAD-mode with recommended output filter, TC = 25 ºC 12
Reset mode, No switching 1
ANALOG INPUTS
VIN Maximum input voltage swing ±2.8 V
IIN Maximum input current -1 1 mA
G Inverting voltage Gain, VOUT/VIN(Master Mode) R1 = 5.6 kΩ, R2 = OPEN 18 dB
R1 = 20 kΩ, R2 = 100 kΩ 24
R1 = 39 kΩ, R2 = 100 kΩ 30
R1 = 47 kΩ, R2 = 75 kΩ 34
Inverting voltage Gain, VOUT/VIN(Slave Mode) R1 = 51 kΩ, R2 = 51 kΩ 18
R1 = 75 kΩ, R2 = 47 kΩ 24
R1 = 100 kΩ, R2 = 39 kΩ 30
R1 = 100 kΩ, R2 = 16 kΩ 34
RIN Input resistance G = 18 dB 48 kΩ
G = 24 dB 24
G = 30 dB 12
G = 34 dB 7.7
OSCILLATOR
fOSC(IO)(1) Nominal, Master Mode FPWM × 6 3.45 3.6 3.75 MHz
AM1, Master Mode 3.06 3.198 3.33
AM2, Master Mode 2.76 2.88 3
VIH High level input voltage 1.88 V
VIL Low level input voltage 1.65 V
EXTERNAL OSCILLATOR (Slave Mode)
fOSC(IO) CLK input on OSCM/OSCP (Slave Mode) 2.3 3.78 MHz

OUTPUT-STAGE MOSFETs
RDS(on) Drain-to-source resistance, low side (LS) TJ = 25 °C, Excludes metallization resistance,
GVDD = 5 V		 70 mΩ
Drain-to-source resistance, high side (HS) 70 mΩ
I/O PROTECTION
Vuvp,AVDD Undervoltage protection limit, AVDD 4 V
Vuvp,AVDD,hyst(2) Undervoltage protection hysteresis, AVDD 0.1 V
Vuvp,PVDD Undervoltage protection limit, PVDD_x 6.4 V
Vuvp,PVDD,hyst(2) Undervoltage protection hysteresis, PVDD_x 0.45 V
OTW Overtemperature warning, OTW_CLIP(2) 115 125 135 °C
OTWhyst(2) Temperature drop needed below OTW temperature for OTW_CLIP to be inactive after OTW event. 20 °C
OTE(2) Overtemperature error 145 155 165 °C
OTEhyst(2) A reset needs to occur for FAULT to be released following an OTE event 20 °C
OTE-OTW(differential)(2) OTE-OTW differential 25 °C
OLPC Overload protection counter fPWM = 600 kHz (1024 PWM cycles) 1.7 ms
IOC, BTL Overcurrent limit protection, speaker output current Nominal peak current in 1Ω load 10 A
IOC, PBTL 20 A
IDCspkr, BTL DC Speaker Protection Current Threshold BTL current imbalance threshold 1.8 A
IDCspkr, PBTL PBTL current imbalance threshold 3.6 A
IOCT Overcurrent response time Time from switching transition to flip-state induced by overcurrent. 150 ns
IPD Output pulldown current of each half Connected when RESET is active to provide bootstrap charge. Not used in SE mode. 3 mA
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage HEAD, OSCM, OSCP,CMUTE, RESET 1.9 V
VIL Low level input voltage 0.8 V
Ilkg Input leakage current 100 μA
OTW/SHUTDOWN (FAULT)
RINT_PU Internal pullup resistance, OTW_CLIP to AVDD, FAULT to AVDD 20 26 32 kΩ
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO = 4 mA 200 500 mV
Device fanout OTW_CLIP, FAULT No external pullup 30 devices
(1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4 : 4.5 : 5
(2) Specified by design.