JAJSGC8B October   2018  – January 2020 TPS25982

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 概要 (続き)
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Protection (UVLO and UVP)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 9.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 9.3.3.2 Circuit Breaker
        3. 9.3.3.3 Active Current Limiting
        4. 9.3.3.4 Short-Circuit Protection
      4. 9.3.4 Overtemperature Protection (OTP)
      5. 9.3.5 Analog Load Current Monitor (IMON)
      6. 9.3.6 Power Good (PG)
      7. 9.3.7 Load Detect/Handshake (LDSTRT)
    4. 9.4 Fault Response
    5. 9.5 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
        2. 10.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 10.2.2.3 Setting the Undervoltage Lockout Set Point
        4. 10.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 10.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 10.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 10.2.2.6 Setting the Load Handshake (LDSTRT) Delay
        7. 10.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        8. 10.2.2.8 Setting the Auto-Retry Delay and Number of Retries
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Optical Module Power Rail Path Protection
        1. 10.3.1.1 Design Requirements
        2. 10.3.1.2 Device Selection
        3. 10.3.1.3 External Component Settings
        4. 10.3.1.4 Voltage Drop
        5. 10.3.1.5 Application Curves
      2. 10.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
        1. 13.1.1.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

RGE
24-Pin QFN
Top View
TPS25982 pinout.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
OUT 17, 18, 19, 20, 21, 22, 23, 24 Power Power Output
IN 1, 2, 3, 16, Pad 1 Thermal / Power Power Input. The exposed pad must be soldered to input power plane uniformly to ensure proper heat dissipation and to maintain optimal current distribution through the device.
GND 4, 5, 14,
Pad 2		 Ground Connect to System Ground
EN/UVLO 6 Analog Input Active High Enable for the device. A resistor divider on this pin from input supply to GND can be used to adjust the Undervoltage Lockout threshold. Do not leave floating.
ITIMER 7 Analog Output A capacitor from this pin to GND sets the overcurrent blanking interval during which the output current can temporarily exceed set current limit (but lower than fast-trip threshold) before the device overcurrent response takes action. Leave this pin open for fastest response to overcurrent events. Refer to ITIMER Functional Mode Summary for more details.
ILIM 8 Analog Output An external resistor from this pin to GND sets the output current limit threshold and fast trip threshold. Do not leave floating.
IMON 9 Analog Output Analog output load current monitor. This pin sources a current proportional to the load current. This can be converted to a voltage signal by connecting an appropriate resistor from this pin to GND.
RETRY_DLY 10 Analog Output A capacitor from this pin to GND sets the time period that has to elapse after a fault shutdown before the device attempts to restart automatically. Connect this pin to GND for latch-off operation (no auto-retries) after a fault. Refer to Fault Response section for more details.
NRETRY 11 Analog Output A capacitor from this pin to GND sets the number of times the part attempts to restart automatically after shutdown due to fault. Connect this pin to GND if the part should retry indefinitely. Refer to Fault Response section for more details.
LDSTRT 12 Analog Input Load Detect/Handshake Signal. A capacitor from this pin to GND sets the time period after PG assertion within which the pin has to be pulled low for the device to remain ON. Connect to GND if the load detect/handshake feature is not used. Refer to Load Detect/Handshake (LDSTRT) section for more details. Do not leave floating.
PG 13 Digital Output Active High Power Good Indication. This pin is asserted when the FET is fully enhanced and output has reached maximum voltage. It is an open drain output that requires an external pull-up resistor to an external supply. This pin remains logic low when VIN < VUVP.
dVdt 15 Analog Output A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest slew rate during start up.