JAJSRQ5A October   2023  – December 2023 TPS3762

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Specifications
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristic
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Reverse Polarity Protection
        2. 7.3.2.2 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (RESET)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: SELV Power Supply Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Setting Voltage Threshold
          2. 8.3.1.2.2 Meeting the Sense and Reset Delay
          3. 8.3.1.2.3 Setting Supply Voltage
          4. 8.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristic

Typical characteristics show the typical performance of the TPS3762 device. Test conditions are TA = 25°C, unless otherwise noted.

GUID-20231206-SS0I-JRXS-ND2P-MZ375ZRG6TX8-low.svgFigure 6-3 Undervoltage Accuracy vs Temperature (VIT = 0.8 V)
GUID-20231206-SS0I-XTRD-574K-RVNRWKZ9LMT9-low.svgFigure 6-5 IDD vs Temperature (RESET = High, VIT = 0.8 V)
GUID-20231212-SS0I-MV3Q-CJXX-CBX6BCPHH6X1-low.svgFigure 6-7 VSENSE vs ISENSE (VDD = 2.7 V)
GUID-20231212-SS0I-VRPN-TTVT-TJFWXSHNTVZK-low.svgFigure 6-9 Open-Drain Active Low VOL vs IRESET (VDD = 2.7 V)
GUID-20231206-SS0I-KH3J-MWTV-CBFPNQCPZM8Z-low.svg
Figure 6-11 Propogation Delay (Undervoltage) vs Temperature (VIT = 0.8V, CTS = Enabled = 50pF)
GUID-20231206-SS0I-PGHJ-KR7L-BCNLCVRBQCHL-low.svgFigure 6-4 Overvoltage Accuracy vs Temperature (VIT = 0.8 V)
GUID-20231212-SS0I-FLZL-JKVN-SV2HRNPSTFQM-low.svgFigure 6-6 IDD vs Temperature (RESET = Low, VIT = 0.8 V)
GUID-20231212-SS0I-MFQL-XSG9-KPHDTCCJTSXS-low.svgFigure 6-8 VSENSE vs ISENSE (VDD = 65 V)
GUID-20231212-SS0I-NWLD-MR1K-4GZRB31RT6MZ-low.svgFigure 6-10 Open-Drain Active Low VOL vs IRESET (VDD = 65 V)
GUID-20231206-SS0I-FJ69-KHFF-BRLGCRRXH7BH-low.svg
Figure 6-12 Propogation Delay (Overvoltage) vs Temperature (VIT = 0.8V, CTS = Enabled = 50pF)