JAJSRQ5A October   2023  – December 2023 TPS3762

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Specifications
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristic
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Reverse Polarity Protection
        2. 7.3.2.2 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (RESET)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: SELV Power Supply Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Setting Voltage Threshold
          2. 8.3.1.2.2 Meeting the Sense and Reset Delay
          3. 8.3.1.2.3 Setting Supply Voltage
          4. 8.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At VDD(MIN) ≤ VDD ≤ VDD(MAX), CTR = CTS = open, output RESET pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5 V, output BIST pull-up resistor RPU_BIST = 10 kΩ, voltage VPU_BIST = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 12 V and VIT = 6.5 V (VIT refers to VITN or VITP).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD Supply Voltage 2.7 65 V
UVLO (1) Undervoltage Lockout VDD rising above VDD (MIN) 2.6 V
UVLO(HYS) (1) Undervoltage Lockout Hysteresis VDD falling below VDD (MIN) 500 mV
VPOR(RESET) Power on Reset Voltage (2)
RESET, Active Low
(Open-Drain)		 VOL(MAX) = 300 mV
IOUT (Sink) = 15 µA
 1.4 V
VPOR(BIST) Power on Reset Voltage (2)
BIST, Active Low
(Open-Drain)		 VOL(MAX) = 300 mV
IOUT (Sink) = 15 µA
 1.4 V
IDD Supply current into VDD pin VIT = 800 mV
VDD (MIN) ≤ VDD ≤ VDD (MAX)
 4 8.1 µA
SENSE (Input)
ISENSE Input current
VIT = 800 mV
 200 nA
VITN  Input Threshold Negative
(Undervoltage)		 VIT = 800 mV (3) -0.9 0.9 %
VITP
Input Threshold Positive 
(Overvoltage)
 		 VIT = 800 mV (3) -0.9 0.9 %
VHYS Hysteresis Accuracy (4) VIT = 0.8 V
VHYS Range = 2%		 1.5 2 2.5 %
RESET (Output)
Ilkg(OD) Open-Drain leakage VRESET = 5.5 V
VITN < VSENSE < VITP		 300 nA
Ilkg(OD) Open-Drain leakage VRESET = 65 V
VITN < VSENSE < VITP		 300 nA
VOL (5) Low level output voltage 2.7 V ≤ VDD ≤ 65 V
IRESET = 2.7 mA
 350 mV
Capacitor Timing (CTS, CTR)
RCTR Internal resistance (CTR) 3.2 4 4.8 MΩ
RCTS Internal resistance (CTS) 3.2 4 4.8 MΩ
Built-in Self-test
Ilkg(BIST) Open-Drain leakage VBIST = 5.5 V
VITN < VSENSE < VITP		 300 nA
Ilkg(BIST) Open-Drain leakage VBIST = 3.3 V
VITN < VSENSE < VITP		 300 nA
VBIST_OL Low level output voltage 2.7 V ≤ VDD ≤ 65 V
IBIST = 5 mA
 300 mV
VBIST_EN BIST_EN pin logic low input 500 mV
VBIST_EN BIST_EN pin logic high input 1300 mV
VBIST_EN/LATCH_CLR LATCH_CLR pin logic low input 500 mV
VBIST_EN/LATCH_CLR LATCH_CLR pin logic high input 1300 mV
(1) When VDD voltage falls below UVLO, RESET is asserted. VDD slew rate ≤ 100 mV / µs
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD slew rate ≤ 100mV/µs
(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation section
(4) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.
(5) For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table