JAJSRQ5A October 2023 – December 2023 TPS3762
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VDD | Supply Voltage | 2.7 | 65 | V | ||
UVLO (1) | Undervoltage Lockout | VDD rising above VDD (MIN) | 2.6 | V | ||
UVLO(HYS) (1) | Undervoltage Lockout Hysteresis | VDD falling below VDD (MIN) | 500 | mV | ||
VPOR(RESET) | Power on Reset Voltage (2) RESET, Active Low (Open-Drain) |
VOL(MAX) = 300 mV IOUT (Sink) = 15 µA |
1.4 | V | ||
VPOR(BIST) | Power on Reset Voltage (2) BIST, Active Low (Open-Drain) |
VOL(MAX) = 300 mV IOUT (Sink) = 15 µA |
1.4 | V | ||
IDD | Supply current into VDD pin | VIT = 800 mV VDD (MIN) ≤ VDD ≤ VDD (MAX) |
4 | 8.1 | µA | |
SENSE (Input) | ||||||
ISENSE | Input current | VIT = 800 mV |
200 | nA | ||
VITN | Input Threshold Negative (Undervoltage) |
VIT = 800 mV (3) | -0.9 | 0.9 | % | |
VITP | Input Threshold Positive (Overvoltage) |
VIT = 800 mV (3) | -0.9 | 0.9 | % | |
VHYS | Hysteresis Accuracy (4) | VIT = 0.8 V VHYS Range = 2% |
1.5 | 2 | 2.5 | % |
RESET (Output) | ||||||
Ilkg(OD) | Open-Drain leakage | VRESET = 5.5 V VITN < VSENSE < VITP |
300 | nA | ||
Ilkg(OD) | Open-Drain leakage | VRESET = 65 V VITN < VSENSE < VITP |
300 | nA | ||
VOL (5) | Low level output voltage | 2.7 V ≤ VDD ≤ 65 V IRESET = 2.7 mA |
350 | mV | ||
Capacitor Timing (CTS, CTR) | ||||||
RCTR | Internal resistance (CTR) | 3.2 | 4 | 4.8 | MΩ | |
RCTS | Internal resistance (CTS) | 3.2 | 4 | 4.8 | MΩ | |
Built-in Self-test | ||||||
Ilkg(BIST) | Open-Drain leakage | VBIST = 5.5 V VITN < VSENSE < VITP |
300 | nA | ||
Ilkg(BIST) | Open-Drain leakage | VBIST = 3.3 V VITN < VSENSE < VITP |
300 | nA | ||
VBIST_OL | Low level output voltage | 2.7 V ≤ VDD ≤ 65 V IBIST = 5 mA |
300 | mV | ||
VBIST_EN | BIST_EN pin logic low input | 500 | mV | |||
VBIST_EN | BIST_EN pin logic high input | 1300 | mV | |||
VBIST_EN/LATCH_CLR | LATCH_CLR pin logic low input | 500 | mV | |||
VBIST_EN/LATCH_CLR | LATCH_CLR pin logic high input | 1300 | mV |