JAJS528B December   2010  – November 2023 TPS53315

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP™ Integrated Circuit with Adaptive On-Time
      2. 6.3.2  Small Signal Model
      3. 6.3.3  Ramp Signal
      4. 6.3.4  Auto-Skip Eco-mode Light Load Operation
      5. 6.3.5  Adaptive Zero Crossing
      6. 6.3.6  Forced Continuous Conduction Mode
      7. 6.3.7  Power Good
      8. 6.3.8  Current Sense and Overcurrent Protection
      9. 6.3.9  Overvoltage and Undervoltage Protection
      10. 6.3.10 UVLO Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable and Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Circuit Diagram
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Step 1: Select Operation Mode and Soft-Start Time
          2. 7.2.1.2.2 Step 2: Select Switching Frequency
          3. 7.2.1.2.3 Step 3: Select the Inductance
          4. 7.2.1.2.4 Step 4: Select Output Capacitors
          5. 7.2.1.2.5 Step 5: Determine the Voltage-Divider Resistance (R1 and R2)
          6. 7.2.1.2.6 Step 6: Select the Overcurrent Resistance (RTRIP)
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application Circuit Diagram With Ceramic Output Capacitors
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Step 1: Select Operation Mode and Soft-Start Time
          2. 7.2.2.2.2 Step 2: Select Switching Frequency
          3. 7.2.2.2.3 Step 3: Select the Inductance
          4. 7.2.2.2.4 Step 4: Select Output Capacitance for Ceramic Capacitors
          5. 7.2.2.2.5 Step 5: Select the Overcurrent Setting Resistance (RTRIP)
        3. 7.2.2.3 External Component Selection When Using All Ceramic Output Capacitors
        4. 7.2.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.7 Power Good

The TPS53315 has power-good output that indicates high when switcher output is within the target. The power-good function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good signal becomes low after two microsecond (2-μs) internal delay. The power-good output is an open drain output and must be pulled up externally.

For the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic before the TPS53315 is powered up, TI recommends the PGOOD be pulled to VREG (either directly or through a resistor divider) because VREG remains low when the device is off.