JAJSBO6B June   2012  – May 2019 TPS54678

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation and Output Current
      3. 8.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Soft-Start Pin
      9. 8.3.9  Sequencing
      10. 8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side Overcurrent Protection
        2. 8.3.11.2 Low-Side Overcurrent Protection
      12. 8.3.12 Safe Start-Up into Prebiased Outputs
      13. 8.3.13 Synchronize Using the RT/CLK Pin
      14. 8.3.14 Power Good (PWRGD Pin)
      15. 8.3.15 Overvoltage Transient Protection
      16. 8.3.16 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Small Signal Model for Loop Response
      2. 8.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 8.4.3 Small Signal Model for Frequency Compensation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Step One: Select the Switching Frequency
        3. 9.2.2.3 Step Two: Select the Output Inductor
        4. 9.2.2.4 Step Three: Choose the Output Capacitor
        5. 9.2.2.5 Step Four: Select the Input Capacitor
        6. 9.2.2.6 Step Five: Choose the Soft-Start Capacitor
        7. 9.2.2.7 Step Six: Select the Bootstrap Capacitor
        8. 9.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
          1. 9.2.2.8.1 Output Voltage Limitations
        9. 9.2.2.9 Step Nine: Select Loop Compensation Components
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Additional Information About Application Curves
          1. 9.2.3.1.1 Efficiency
          2. 9.2.3.1.2 Voltage Ripple Measurements
          3. 9.2.3.1.3 Start-Up and Shutdown Waveforms
          4. 9.2.3.1.4 Hiccup Mode Current Limit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation Estimate
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Step Three: Choose the Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. Along with the inductor, the output capacitor determines the output voltage ripple, and also how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these two criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not due to limited control speed. The regulator is temporarily not able to supply sufficient change in output current if there is a large, fast increase or decrease in the current needs of the load such as transitioning from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change, or conversely, absorb the excess current from the inductor. Because the output voltage is less than half the input voltage, the worst-case deviation in output voltage occurs when the load has an extremely rapid reduction in current, or a load dump. The desired specification is a 50% or 3-A load step, and a resulting voltage deviation of no more than 5%, or 60mV. When a load dump occurs, the excess stored current in the inductor will tend to charge the output capacitors, and the best the converter can achieve to limit the increase in output voltage is to fold back the duty cycle to zero. Under these circumstances, the amount of rise in output voltage is defined by the energy from the choke being fully absorbed by the capacitor bank. Equation 18 through Equation 20 can be used to calculate the required capacitor bank value.

For this example, the transient load response is specified as a 5% change in Vout for a 50% load step from 3 A to 0 A. So, ΔIOUT = 3 A and ΔVOUT = 0.05 × 1.2 = 0.06 V. Using these numbers gives a minimum capacitance of 73.2 μF. This calculation does not take the ESR of the output capacitor into account in the output voltage change, and it does not account for latency in control loop speed. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Equation 18. TPS54678 Eq18_SLVSBF3.gif
Equation 19. TPS54678 Eq19_SLVSBF3.gif

Solving for C:

Equation 20. TPS54678 Eq20_SLVSBF3.gif

This 73.17 µF defines the minimum capacitance required to meet the transient spec; however, because the control loop speed is finite, more capacitance than this is required to meet desired performance.

Equation 21 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 60 mV. Under this requirement, Equation 21 yields 13.33 µF.

Equation 21. TPS54678 Eq21_SLVSBF3.gif

where

  • FSW is the switching frequency,
  • VRIPPLE is the maximum allowable output voltage ripple,
  • and Iripple is the inductor ripple current.

Equation 22 calculates the maximum ESR for the capacitor bank to meet the output voltage ripple specification. Equation 22 indicates the ESR should be less than 37.5 mΩ. In this case, the ESR of the ceramic capacitor bank is less than 37.5 mΩ.

Equation 22. TPS54678 Eq22_SLVSBF3.gif

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases the minimum value calculated in Equation 20. For this example, five 47-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used. The estimated capacitance after derating is 5 × 47 μF × 0.9 = 211.5 μF.