JAJSMU6C June   2012  – September 2021 TPS54719

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency PWM Control
      2. 7.3.2 Slope Compensation And Output Current
      3. 7.3.3 Bootstrap Voltage (Boot) And Low Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
      6. 7.3.6 Adjusting The Output Voltage
      7. 7.3.7 Enable and Adjusting Undervoltage Lockout
      8. 7.3.8 Slow Start/Tracking Pin
      9. 7.3.9 Sequencing
    4. 7.4 Device Functional Modes
      1. 7.4.1  Constant Switching Frequency And Timing Resistor (RT Pin)
      2. 7.4.2  Overcurrent Protection
      3. 7.4.3  Frequency Shift
      4. 7.4.4  Reverse Overcurrent Protection
      5. 7.4.5  Power Good (PWRGD Pin)
      6. 7.4.6  Overvoltage Transient Protection
      7. 7.4.7  Thermal Shutdown
      8. 7.4.8  Small Signal Model For Loop Response
      9. 7.4.9  Simple Small Signal Model For Peak Current Mode Control
      10. 7.4.10 Small Signal Model For Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Frequency, 1.8-V Output Power Supply Design With Adjusted UVLO
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Selecting The Switching Frequency
        2. 8.2.3.2 Output Inductor Selection
        3. 8.2.3.3 Output Capacitor
        4. 8.2.3.4 Input Capacitor
        5. 8.2.3.5 Slow-Start Capacitor
        6. 8.2.3.6 Bootstrap Capacitor Selection
        7. 8.2.3.7 Undervoltage Lockout Set Point
        8. 8.2.3.8 Output Voltage And Feedback Resistors Selection
        9. 8.2.3.9 Compensation
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open-drain or collector output of a power on reset pin of another device. Figure 7-3 shows the sequential method. The power good is coupled to the EN pin on the TPS54719, which enables the second power supply once the primary supply reaches regulation.

Ratio-metric start-up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time, the pullup current source must be doubled in Equation 4. The ratio metric method is illustrated in Figure 7-5.

GUID-93AA5AF4-0A03-416D-84D1-A58A4C9629B0-low.gifFigure 7-3 Sequential Start-Up Sequence
GUID-D2CEC01F-6402-4D39-A024-6FAB47F60A59-low.gifFigure 7-5 Schematic For Ratio-Metric Start-Up Sequence
GUID-1004B163-7496-46BE-B8DD-22DD8AA31D8F-low.gifFigure 7-4 Sequential Start-Up Using EN And PWRGD
GUID-414D50A1-A8B9-4FE3-8849-40CE75F1CA36-low.gifFigure 7-6 Ratio-Metric Start-Up With VOUT1 Leading VOUT2

Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 7-5 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after, or at the same time as VOUT1. Equation 7 is the voltage difference between VOUT1 and VOUT2. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 5 through Equation 7 for ΔV. Equation 7 will result in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 0.87 V for a complete handoff to the internal voltage reference as shown in Figure 7-6.

Equation 5. GUID-F4393F70-9613-438C-B967-B3488D5737EB-low.gif
Equation 6. GUID-6D6021CD-E7BD-4F65-88B5-24C83728033B-low.gif
Equation 7. GUID-E76388B0-AF3C-4708-8BC3-B52C85CE9530-low.gif

where:

  • VOUT2 is the regulated output of IC2
  • VOUT1 is the output of IC1 at the moment IC2 just reaches its regulation
GUID-ABB80A8A-A399-4544-9629-D95F8289B0A4-low.gifFigure 7-7 Schematic For Ratio-Metric Start-Up Sequence
GUID-1A4C4818-E89C-41EF-9553-593721B2E8BA-low.gifFigure 7-8 Ratio-Metric Start-Up Using Coupled SS/TR Pins