JAJSNP4A May   2023  – February 2024 TPS54KB20

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using External Bias On the VCC Pin
      2. 6.3.2  Enable
      3. 6.3.3  Adjustable Soft Start
      4. 6.3.4  Power Good
      5. 6.3.5  Output Voltage Setting
      6. 6.3.6  Remote Sense
      7. 6.3.7  D-CAP4 Control
      8. 6.3.8  Multifunction Select (MSEL) Pin
      9. 6.3.9  Low-side MOSFET Zero-Crossing
      10. 6.3.10 Current Sense and Positive Overcurrent Protection
      11. 6.3.11 Low-side MOSFET Negative Current Limit
      12. 6.3.12 Overvoltage and Undervoltage Protection
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Powering the Device From a Single Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Output Voltage Setting Point
        2. 7.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 7.2.2.3  Choose the Inductor
        4. 7.2.2.4  Set the Current Limit (ILIM)
        5. 7.2.2.5  Choose the Output Capacitor
        6. 7.2.2.6  RAMP Selection
        7. 7.2.2.7  Choose the Input Capacitors (CIN)
        8. 7.2.2.8  Soft-Start Capacitor (SS Pin)
        9. 7.2.2.9  EN Pin Resistor Divider
        10. 7.2.2.10 VCC Bypass Capacitor
        11. 7.2.2.11 BOOT Capacitor
        12. 7.2.2.12 RC Snubber
        13. 7.2.2.13 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.10 Current Sense and Positive Overcurrent Protection

For a buck converter, during the on-time of the high-side MOSFET, the switch current increases at a linear rate determined by the input voltage, output voltage, on-time, and output inductor value. During the on-time of the low-side MOSFET, the current decreases linearly. The average value of the switch current equals the load current.

The output overcurrent limit (OCL) in the device is implemented using a cycle-by-cycle valley current detect control circuit. The inductor current is monitored during the on-time of the low-side MOSFET by measuring the low-side MOSFET drain-to-source current. If the measured drain-to-source current of the low-side MOSFET is above the current limit threshold, the low-side MOSFET stays ON until the current level becomes lower than the current limit threshold. This type of behavior reduces the average output current sourced by the device.

During an overcurrent condition, the current to the load exceeds the current to the output capacitors. Thus, the output voltage tends to decrease. Eventually, when the output voltage falls below the undervoltage-protection threshold (80%), the UVP comparator detects the fall and shuts down the device after a wait time of 70µs. Depending on the part number, the device either hiccups or latches off, as described in Overvoltage and Undervoltage Protection.

Figure 6-7 shows the cycle-by-cycle valley current limit behavior as well as the wait time before the device shuts down.

GUID-20240124-SS0I-TGNC-LB1J-JTXLD1CR4MSC-low.svg Figure 6-7 Overcurrent Protection

If an OCL condition happens during start-up, the device still has cycle-by-cycle current limit based on low-side valley current. After soft start is finished, the UV event which is caused by the OCL event shuts down the device after a wait time of 70µs. Depending on the part number, the device either hiccups or latches off after the UV is tripped as described in Overvoltage and Undervoltage Protection.

The resistor, RILIM connected from the ILIM pin to AGND sets current limit threshold. TI recommends a ±1% tolerance resistor because a worse tolerance resistor provides less accurate OCL threshold. Equation 5 calculates the RILIM for a given overcurrent limit threshold on the device. Equation 6 calculates the overcurrent limit threshold for a given RILIM value.

To protect the device from an unexpected connection to the ILIM pin, an internal fixed OCL clamp is implemented. This internal OCL clamp limits the maximum valley current on the low-side MOSFET when the ILIM pin has too small of a resistance to AGND, or is accidentally shorted to ground. TI does not recommend designing with an RILIM < 4.32kΩ.

Equation 5. R I L I M = K O C L I O C L I M - 1 2 × V I N - V O U T × V O U T V I N × 1 L × f S W

where

  • IOCLIM is overcurrent limit threshold for load current in A
  • RILIM is ILIM resistor value in Ω
  • KOCL is a constant of 120 × 103 for the calculation
  • VIN is input voltage value in V
  • VOUT is output voltage value in V
  • L is output inductor value in µH
  • fSW is switching frequency in MHz
Equation 6. I O C L I M = K O C L R I L I M + 1 2 × V I N - V O U T × V O U T V I N × 1 L × f S W