JAJSNP4A May   2023  – February 2024 TPS54KB20

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using External Bias On the VCC Pin
      2. 6.3.2  Enable
      3. 6.3.3  Adjustable Soft Start
      4. 6.3.4  Power Good
      5. 6.3.5  Output Voltage Setting
      6. 6.3.6  Remote Sense
      7. 6.3.7  D-CAP4 Control
      8. 6.3.8  Multifunction Select (MSEL) Pin
      9. 6.3.9  Low-side MOSFET Zero-Crossing
      10. 6.3.10 Current Sense and Positive Overcurrent Protection
      11. 6.3.11 Low-side MOSFET Negative Current Limit
      12. 6.3.12 Overvoltage and Undervoltage Protection
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Powering the Device From a Single Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Output Voltage Setting Point
        2. 7.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 7.2.2.3  Choose the Inductor
        4. 7.2.2.4  Set the Current Limit (ILIM)
        5. 7.2.2.5  Choose the Output Capacitor
        6. 7.2.2.6  RAMP Selection
        7. 7.2.2.7  Choose the Input Capacitors (CIN)
        8. 7.2.2.8  Soft-Start Capacitor (SS Pin)
        9. 7.2.2.9  EN Pin Resistor Divider
        10. 7.2.2.10 VCC Bypass Capacitor
        11. 7.2.2.11 BOOT Capacitor
        12. 7.2.2.12 RC Snubber
        13. 7.2.2.13 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

TJ = –40°C to +125°C, VVCC = 3V (internal), VVIN = 4V to 16V. Typical values are at TJ = 25°C and VVIN = 12V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current Non-switching, VEN = 2V, VFB = VFB_REG + 10mV, no external bias on VCC pin 940 1200 µA
IQ(VIN) VIN quiescent current with external VCC bias VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin 230 350 µA
IQ(VCC) VCC quiescent current VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin 820 1000 µA
ISD(VIN) VIN shutdown supply current VIN = 12V, VEN = 0V, no external bias on VCC pin 9 20 µA
ISD(VCC) VCC shutdown current VEN = 0V, VIN = 0V, 3.3V external bias on VCC pin 90 140 µA
IVCC VCC external bias current TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, RMSEL = 10.5kΩ, fSW = 800kHz, 3.3V external bias on VCC pin 12 mA
TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, RMSEL = 13.3kΩ, fSW = 1100kHz, 3.3V external bias on VCC pin 16 mA
TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, RMSEL = 30.1kΩ, fSW = 1400kHz, 3.3V external bias on VCC pin 20.5 mA
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.87 3.95 V
VINUVLO(F) VIN UVLO falling threshold VIN falling 3.60 3.70 V
VINUVLO(H) VIN UVLO hysteresis 0.17 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.18 1.23 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.95 1 V
VEN(H) EN voltage hysteresis 0.18 V
EN internal pull-down resistance EN pin to AGND 0.74 1 1.27 MΩ
VENSTB(R) EN standby rising threshold EN rising, enable internal LDO, no switching 0.75 1.0 V
VENSTB(F) EN standby falling threshold EN falling, disable internal LDO 0.5 0.6 V
INTERNAL LDO (VCC)
VVCC Internal LDO output voltage Non-switching, IVCC = 25mA 2.82 2.94 3.05 V
IVCC Internal LDO short-circuit current limit VVIN = 10V 100 275 mA
VCCUVLO(R) VCC UVLO rising threshold VVIN = 4V 2.7 2.82 V
VCCUVLO(F) VCC UVLO falling threshold VVIN = 4V 2.45 2.55 V
VCCUVLO(H) VCC UVLO hysteresis VVIN = 4V 0.15 V
FB threshold to turn off VCC LDO EN high to low 25 50 85 mV
REFERENCE VOLTAGE (FB)
VFB_REG Feedback regulation voltage TPS54KB20 and TPS54KB22 895.5 900 904.5 mV
VFB_REG Feedback regulation voltage TPS54KB21 and TPS54KB23 497.5 500 502.5 mV
IFB(LKG) FB input leakage current VFB = VFB_REG 160 nA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
IGOSNS Leakage current out of GOSNS pin VGOSNS - VAGND = 100mV 80 µA
VICM GOSNS common mode voltage for regulation VGOSNS versus VAGND –0.1 0.1 V
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, FCCM operation VVIN = 12V, VOUT = 3.3V, RMSEL = 10.5kΩ (FCCM), No load 680 800 920 kHz
VVIN = 12V, VOUT = 3.3V, RMSEL = 24.9kΩ (FCCM), No load 910 1070 1230 kHz
VVIN = 12V, VOUT = 3.3V, RMSEL = 48.7kΩ (FCCM), No load 1150 1350 1550 kHz
STARTUP
ISS Soft-start charge current VSS = 0V 26 36 45 µA
VSS(DONE) Soft-start voltage threshold for soft-start done TPS54KB21 and TPS54KB23 1 V
VSS(DONE) Soft-start voltage threshold for soft-start done TPS54KB20 and TPS54KB22 1.2 V
EN HIGH to start of switching delay CSS = 33nF, Internal VCC, CVCC = 2.2µF, RMSEL = 158kΩ, Measured from EN high to VSS = 50mV 740 µs
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance VBOOT-SW = 3.0V 5.8 mΩ
RDSON(LS) Low-side MOSFET on-resistance VVCC = 3.3V 2.3 mΩ
tON(min) Minimum ON pulse width 40 ns
tOFF(min) Minimum OFF pulse width (1) 130 160 ns
BOOT CIRCUIT
IBOOT(LKG) Leakage current into BOOT pin VVIN = 12V, VBOOT-SW = 3V, Enabled, Not switching 23 31 µA
OVERCURRENT PROTECTION
OC limit high clamp Valley current on LS FET, 0Ω ≤ RILIM ≤ 4.32kΩ 25 27.5 A
KOCL Constant for RILIM equation 120000 A×Ω
ILS(OC) Low-side valley current limit, open loop Valley current on LS FET, RILIM = 4.32kΩ  25 27.5 A
Valley current on LS FET, RILIM = 5.36kΩ 17.9 22.1 26.5 A
Valley current on LS FET, RILIM = 7.32kΩ 13.0 16.2 19.6 A
Valley current on LS FET, RILIM = 10.7kΩ 8.5 11.1 13.7 A
Valley current on LS FET, RILIM = 20kΩ 4.0 5.9 7.9 A
ILS(NOC) Low-side negative current limit, open loop Sinking current limit on LS FET –10 –7.5 A
RILIM ILIM pin resistance range 0 20 kΩ
IZC Zero-cross detection current threshold to enter DCM, open loop VIN = 12V –700 mA
IZC(HYS) Zero-cross detection current threshold hysteresis after entering DCM, open loop VIN = 12V 1000 mA
OUTPUT OVP AND UVP
VOVP Overvoltage-protection (OVP) threshold voltage TPS54KB21 and TPS54KB23, VFB rising 113% 116% 119%
VUVP Undervoltage-protection (UVP) threshold voltage TPS54KB21 and TPS54KB23, VFB falling 76% 79% 82%
VOVP Overvoltage-protection (OVP) threshold voltage TPS54KB20 and TPS54KB22, VFB rising 115% 118% 121%
VUVP Undervoltage-protection (UVP) threshold voltage TPS54KB20 and TPS54KB22, VFB falling 77% 80% 83%
tOVPDLY OVP delay With 100mV overdrive 400 ns
tUVPDLY UVP filter delay 70 µs
Hiccup wait time TPS54KB22 and TPS54KB23 7 x tSS ms
POWER GOOD
VPGTH(RISE_OV) Power-good threshold TPS54KB20 and TPS54KB22, FB rising, PG high to low 115% 118% 121%
VPGTH(RISE_UV) Power-good threshold TPS54KB20 and TPS54KB22, FB rising, PG low to high 89% 92.5% 95%
VPGTH(FALL_UV) Power-good threshold TPS54KB20 and TPS54KB22, FB falling, PG high to low 77% 80% 83%
VPGTH(RISE_OV) Power-good threshold TPS54KB21 and TPS54KB23, FB rising, PG high to low 113% 116% 119%
VPGTH(RISE_UV) Power-good threshold TPS54KB21 and TPS54KB23, FB rising, PG low to high 91%
VPGTH(FALL_UV) Power-good threshold TPS54KB21 and TPS54KB23, FB falling, PG high to low 79%
PG delay going from low to high during startup 1.3 ms
PG delay going from high to low 4 6.2 µs
IPG(LKG) PG pin leakage current when open drain output is high VPG = 6V 7 µA
PG pin output low-level voltage IPG = 7mA 500 mV
PG pin output low-level when VIN and VCC are low   VVIN = 0V, VVCC = 0V, VEN = 0V, IPG = 25µA 650 mV
PG pin output low-level when VIN and VCC are low   VVIN = 0V, VVCC = 0V, VEN = 0V, IPG = 250µA 800 mV
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 150 170 °C
TJ(HYS) Thermal shutdown hysteresis (1) 13 °C
OUTPUT DISCHARGE
Output discharge resistor on SW pin VIN = 12V, VSW = 1V, power conversion disabled 100 Ω
(1) This parameter is provided for reference only, and do not consitute part of TI's published device specifications for purpose of TI's product warranty.