7.4 User Selections
After the V5A, VDD, and VINTF voltages are applied to the controller and all these voltage levels are above their respective UVLO levels, the following information is latched and cannot be changed during operation. The defines the values of the selections.
- Operating Frequency. The resistor from FREQ-P pin to GND sets the switching frequency. See the Detailed Design Procedure for the resistor settings corresponding to each frequency selection. Note that the operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed based on the input voltage (at the VBAT pin) and output voltage (set by VID). The OFF time varies based on various factors such as load and power-stage components.
- Overcurrent Protection (OCP) Level. The resistor from OCP-I to GND sets the OCP level of the CPU channel. See the Detailed Design Procedure for the resistor settings corresponding to each OCP level.
- IMON Gain. The resistors from IMON to OCP-I and OCP-I to GND set the DC load current monitor (IMON) gain.
- Slew Rate. The SetVID fast slew rate is set by the resistor from SLEWA pin to GND. See the Detailed Design Procedure for the resistor settings corresponding to each slew rate setting.
- Base Address. The voltage on SLEWA pin sets the device base address.
- Ramp Selection. The resistor from RAMP to GND sets the ramp compensation level. See the Detailed Design Procedure for the resistor settings corresponding to each ramp level.
- Overshoot Reduction (OSR) Level. The resistor from O-USR to GND sets the OSR level. Detailed Design Procedure provides all the possible selections for OSR.
- Undershoot Reduction Level (USR) The voltage on O-USR pin sets the USR level. Detailed Design Procedure provides all the possible selections for USR.
- Active Phases. Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V supply and tie the CSN2 and CSN3 pins to GND.