JAJSEF3B january   2018  – june 2023 TPS61280D , TPS61280E , TPS61281D

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 I2C Interface Timing Characteristics #GUID-BD85FD7C-B9AF-4F5D-9DFF-CD61365A592A/SLVS5401494
    7. 8.7 I2C Timing Diagrams
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Voltage Scaling Management (VSEL)
      2. 9.3.2 Spread Spectrum, PWM Frequency Dithering
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
      2. 9.4.2 Pass-Through Mode
      3. 9.4.3 Mode Selection
      4. 9.4.4 Current Limit Operation
      5. 9.4.5 Start-Up and Shutdown Mode
      6. 9.4.6 Undervoltage Lockout
      7. 9.4.7 Thermal Shutdown
      8. 9.4.8 Fault State and Power-Good
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description (TPS61280D/E)
      2. 9.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 9.5.3 HS-Mode Protocol
      4. 9.5.4 TPS6128xD/E I2C Update Sequence
    6. 9.6 Register Maps
      1. 9.6.1  Slave Address Byte
      2. 9.6.2  Register Address Byte
      3. 9.6.3  I2C Registers, E2PROM, Write Protect
      4. 9.6.4  E2PROM Configuration Parameters
      5. 9.6.5  CONFIG Register [reset = 0x01]
      6. 9.6.6  VOUTFLOORSET Register [reset = 0x02]
      7. 9.6.7  VOUTROOFSET Register [reset = 0x03]
      8. 9.6.8  ILIMSET Register [reset = 0x04]
      9. 9.6.9  Status Register [reset = 0x05]
      10. 9.6.10 E2PROMCTRL Register [reset = 0xFF]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS61281D with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280D with default I2C Configuration)
        1. 10.2.1.1 Design Requirement
        2. 10.2.1.2 Detailed Design Parameters
          1. 10.2.1.2.1 Inductor Selection
          2. 10.2.1.2.2 Output Capacitor
          3. 10.2.1.2.3 Input Capacitor
          4. 10.2.1.2.4 Checking Loop Stability
        3. 10.2.1.3 Application Performance Curves
      2. 10.2.2 TPS61282D with 2.5V-4.35 VIN, 2000 mA Output Current (TPS61280D with I2C Programmable)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedures
        3. 10.2.2.3 Application Performance Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Information
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6.8 ILIMSET Register [reset = 0x04]

Memory location: 0x04

Figure 9-17 ILIMSET Register
76543210
RESERVEDILIM OFFSoft-startILIM
R/WR/WR/WR/WR/WR/WR/WR/W
Stored in E2
NNNYYYYY
Table 9-7 ILIMSET Register Field Descriptions
Bit Field Type Reset (TPS61280D) Reset (TPS61280E) Description
7:6 RESERVED R/W 0 0 Reserved bit.
This bits is reserved for future use. During write operations data intended for this bit is ignored, and during read operations 0 is returned.
5 ILIM OFF R/W 0 0 Enable/Disable Current Limit
0 : Current Limit Enabled
1 : Current Limit Disabled
4 Soft-start R/W 1 1 Soft-start selection bit.
0: DC/DC boost soft-start current is limited per ILIM bit settings
1: DC/DC boost soft-start current is limited to ca. 1250mA inductor valley current
3 ILIM R/W 1 1 Inductor valley current limit in dc/dc boost mode (COUTRNG bit = 0)(1).
1000: 1500mA
1001: 2000mA
1010: 2500mA
1011: 3000mA
1100: 3500mA
1101: 4000mA
1110: 4500mA
1111: 5000mA
2 R/W 0 1
1 R/W 1 1
0 R/W 1 1
(1) Refer to Section 9.4.5 Mode section for additional information.