JAJSH47 March   2019 TPS65653-Q1

PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.  

  1. 特長
    1.     概略回路図
  2. アプリケーション
  3. 概要
    1.     DC/DC 効率と出力電流との関係
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
        4. 8.3.1.4 Spread-Spectrum Mode
      2. 8.3.2 Sync Clock Functionality
      3. 8.3.3 Power-Up
      4. 8.3.4 Regulator Control
        1. 8.3.4.1 Enabling and Disabling Regulators
        2. 8.3.4.2 Changing Output Voltage
      5. 8.3.5 Enable and Disable Sequences
      6. 8.3.6 Device Reset Scenarios
      7. 8.3.7 Diagnosis and Protection Features
        1. 8.3.7.1 Power-Good Information (PGOOD pin)
          1. 8.3.7.1.1 PGOOD Pin Gated mode
          2. 8.3.7.1.2 PGOOD Pin Continuous Mode
        2. 8.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 8.3.7.2.1 Output Power Limit
          2. 8.3.7.2.2 Thermal Warning
        3. 8.3.7.3 Protection (Regulator Disable)
          1. 8.3.7.3.1 Short-Circuit and Overload Protection
          2. 8.3.7.3.2 Overvoltage Protection
          3. 8.3.7.3.3 Thermal Shutdown
        4. 8.3.7.4 Fault (Power Down)
          1. 8.3.7.4.1 Undervoltage Lockout
      8. 8.3.8 Operation of the GPO Signals
      9. 8.3.9 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto-Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  DEV_REV
        2. 8.6.1.2  OTP_REV
        3. 8.6.1.3  BUCK0_CTRL_1
        4. 8.6.1.4  BUCK0_CTRL_2
        5. 8.6.1.5  BUCK1_CTRL_1
        6. 8.6.1.6  BUCK1_CTRL_2
        7. 8.6.1.7  BUCK0_VOUT
        8. 8.6.1.8  BUCK1_VOUT
        9. 8.6.1.9  BUCK0_DELAY
        10. 8.6.1.10 BUCK1_DELAY
        11. 8.6.1.11 GPO_DELAY
        12. 8.6.1.12 GPO2_DELAY
        13. 8.6.1.13 GPO_CTRL
        14. 8.6.1.14 CONFIG
        15. 8.6.1.15 PLL_CTRL
        16. 8.6.1.16 PGOOD_CTRL_1
        17. 8.6.1.17 PGOOD_CTRL_2
        18. 8.6.1.18 PG_FAULT
        19. 8.6.1.19 RESET
        20. 8.6.1.20 INT_TOP_1
        21. 8.6.1.21 INT_TOP_2
        22. 8.6.1.22 INT_BUCK
        23. 8.6.1.23 TOP_STAT
        24. 8.6.1.24 BUCK_STAT
        25. 8.6.1.25 TOP_MASK_1
        26. 8.6.1.26 TOP_MASK_2
        27. 8.6.1.27 BUCK_MASK
        28. 8.6.1.28 SEL_I_LOAD
        29. 8.6.1.29 I_LOAD_2
        30. 8.6.1.30 I_LOAD_1
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Inductor Selection
        2. 9.2.1.2 Buck Input Capacitor Selection
        3. 9.2.1.3 Buck Output Capacitor Selection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

RHD Package
28-Pin VQFN With Thermal Pad
Top View
TPS65653-Q1 sn1805040-pinmap-diagram.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NUMBER NAME
1 NC O Unused. Leave this pin floating.
2 FB_B0 A Output voltage feedback (positive) for Buck 0
3 FB_B1 A Output voltage feedback (positive) for Buck 1
4 AGND G Ground
5 VANA P/I Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.
6 EN D/I Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin floating.
7 NC O Unused. Leave this pin floating.
8 VIN I Unused. Connect this pin to VANA.
9 nINT D/O Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground.
10 CLKIN D/I/O External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is not used, leave the pin floating.
11, 12 VIN_B1 P/I Input for Buck 1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
13, 14 SW_B1 P/O Buck 1 switch node. If the Buck 1 is not used, leave the pin floating.
15, 16 PGND_B1 P/G Power ground for Buck 1
17 SCL D/I Serial interface clock input for I2C access. Connect a pullup resistor. If the I2C interface is not used, connect the pin to Ground.
18 SDA D/I/O Serial interface data input and output for I2C access. Connect a pullup resistor. If the I2C interface is not used, connect the pin to Ground.
19 SGND G Ground
20, 21 PGND_B0 P/G Power ground for Buck 0
22, 23 SW_B0 P/O Buck 0 switch node. If the Buck 0 is not used, leave the pin floating.
24, 25 VIN_B0 P/I Input for Buck 0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
26 GPO D/O General-purpose digital output. If the pin is not used, leave the pin floating.
27 PGOOD D/O Power-good indication signal. If the pin is not used, leave the pin floating.
28 VIN I Unused. Connect this pin to VANA.
Thermal Pad Connect to PCB ground plane using multiple vias for good thermal performance.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin