JAJSGZ7A May   2015  – February 2019 UC1845A-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      VREF放射線ドリフト曲線
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 UVLO
      2. 9.3.2 Reference
      3. 9.3.3 Totem-Pole Output
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Oscillator
        2. 10.2.2.2 Current Sensing and Limiting
        3. 10.2.2.3 Error Amplifier
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Feedback Traces
      2. 12.1.2 Input/Output Capacitors
      3. 12.1.3 Compensation Components
      4. 12.1.4 Traces and Ground Planes
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 UVLO

The UVLO circuit ensures that VCC is adequate to make the UC1845A-SP fully operational before enabling the output stage. Figure 5 shows that the UVLO turnon and turnoff thresholds are fixed internally at 8.5 V and 7.9 V, respectively. The 0.6-V hysteresis prevents VCC oscillations during power sequencing.

Figure 6 shows supply current requirements. Start-up current is < 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as shown in Figure 7. During normal circuit operation, VCC is developed from auxiliary winding, WAux, with D1 and CIN. However, at start-up, CIN must be charged to 16 V through RIN. With a start-up current of 1 mA, RIN can be as large as 100 kΩ and still charge CIN when VAc = 90-V RMS (low line). Power dissipation in RIN would then be less than 350 mW even under high line (VAc = 130-V RMS) conditions.

During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off.

UC1845A-SP UVLO_LUSC14.gifFigure 5. UVLO Turnon TurnOff Threshold
UC1845A-SP UVLO_output_driver_LUSC14.gif
During UVLO, the output driver is biased to sink minor amounts of current.
Figure 6. Supply Current Requirements
UC1845A-SP providing_pwr_LUSC14.gifFigure 7. Providing Power to the UC1845A-SP