JAJSOG3 December   2023 UCC28750

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Descriptions
      1. 7.3.1 VDD - Input Bias
      2. 7.3.2 DRV - Gate Drive Out
      3. 7.3.3 CS - Current Sensing
      4. 7.3.4 FB - Feedback
      5. 7.3.5 FLT - Fault
      6. 7.3.6 GND - Ground Return
    4. 7.4 Feature Description
      1. 7.4.1 Soft Start
      2. 7.4.2 Control Law
      3. 7.4.3 Frequency Dithering
      4. 7.4.4 Fault Protections
        1. 7.4.4.1 VDD Overvoltage and Undervoltage Lockout
        2. 7.4.4.2 Internal Overtemperature Protection
        3. 7.4.4.3 Output Overpower Protection
        4. 7.4.4.4 Output Short-Circuit Protection
        5. 7.4.4.5 FLT Pin Protections
      5. 7.4.5 Slope Compensation
    5. 7.5 Device Functional Modes
      1. 7.5.1 Off
      2. 7.5.2 Startup
      3. 7.5.3 On
      4. 7.5.4 Fault
      5. 7.5.5 Disabled
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Bulk Capacitance with Minimum Bulk Voltage
        2. 8.2.3.2 Transformer Turns Ratio and Inductance
        3. 8.2.3.3 Current Sense and Slope Compensation Network
        4. 8.2.3.4 Output Capacitors
        5. 8.2.3.5 VDD Capacitance, CVDD
      4. 8.2.4 Application Performance Plots
        1. 8.2.4.1 Startup
        2. 8.2.4.2 Load Transients
        3. 8.2.4.3 Q1 Drain Voltage Evaluation
      5. 8.2.5 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Transformer Turns Ratio and Inductance

The transformer design process starts with selecting a switching frequency and maximum duty cycle. With the UCC287502, the switching frequency is set to 65kHz for the max load operation. The maximum duty cycle can safely be chosen to be above 50% as the UCC28750 is a flexible controller capable of DCM and CCM operation while handling sub-harmonic oscillation with the internal slope compensation feature.

Equation 8. D max,initial = 65 %

With the maximum duty cycle for the design set, the secondary to primary transformer turns ratio, NS to NP, can be chosen by using the boundary mode condition equations to simplify the design process. The turns ratio selection is an iterative process, and the primary switching MOSFET device maximim drain-to-source voltage must be accounted for when designing the transformer.

The turns ratio is initially chosen by using the minimum input voltage and the maximum duty cycle value. This scenario has the highest average current the transformer and switching device must handle, and is why in most of the equations use this worst case for determining the inductance and turns ratio of the transformer. Setting NP to 1 turn, the secondary turns in the turns ratio is determined with Equation 9

Equation 9. N S = V o × ( 1 - D max,initial ) V bulk,min × D max,initial

The 650V drain-to-source (VDS) rated MOSFET is a popular device used in flyback topologies, especially those with a universal input requirement (80V,AC to 265V,AC). The reflected voltage, the voltage seen by the transformer during the secondary conduction time, must be below the MOSFET VDS rating, with additional margin for the leakage spike. The leakage spike is additional ringing that occurs in flyback designs due to the MOSFET output capacitance and transformer leakage inductance.

Equation 10. V margin = 0.8 × V DS
Equation 11. V reflected = V bulk,max + N P N S × V o
Equation 12. V reflected < V margin

Combining Equation 10, Equation 11, Equation 12, and solving for the turns ratio results in a constraint for the turns ratio:

Equation 13. N P N S < V margin - V bulk,max V o

A turns ratio of 1:6 is chosen for this design concept. The duty cycle can be iterated on and a new maximum duty cycle, Dmax, can be selected with the new turns ratio, and comes out to be around 65%, which is what the max was initially set to.

Equation 14. D max = Vo N S N P × Vbulk,min + Vo

With the selected turns ratio, maximum duty cycle, input range, and output power range, the magnetizing inductance value can be calculated using equation Equation 15, and comes out to be approximately 480μH. The equation for the inductance is derived by using the boundary mode equations and equating the average input power equal to the average output power, with a factor for the efficiency.

Equation 15. L = V bulk,min 2 × D max 2 × T sw × η 2 × P out,max × K ccm

Where

  • η as the assumed efficiency of the flyback
  • Tsw as the normal operation switching period
    • In this case 15μs , as the device variant for this application design is a 65kHz variant
  • Kccm is factor from 0.1 to 1 that determines the percentage of output max output power at the boundary condition that the flyback enters into the CCM state