DLPU113A December   2021  – April 2022 DLP2021-Q1

 

  1.   Trademarks
  2. 1DLP2021-Q1 Electronics EVM Overview
    1. 1.1 Introduction
    2. 1.2 What is in the DLP2021-Q1 Light Engine EVM
      1. 1.2.1 Formatter Subsystem
      2. 1.2.2 Illumination Subsystem
      3. 1.2.3 Light Engine
      4. 1.2.4 Cables
    3. 1.3 Non-Optical Specifications
      1. 1.3.1 Electrical Specifications
      2. 1.3.2 Component Temperature Ratings
      3. 1.3.3 LED Driver Design
      4. 1.3.4 Video Specification
  3. 2Quick Start
    1. 2.1 Kit Assembly Instructions
    2. 2.2 Software Installation
    3. 2.3 Power-Up
    4. 2.4 Select Display Content
    5. 2.5 LED Driver
  4. 3Optics and Mechanics
  5. 4Software
    1. 4.1 DLP Composer
      1. 4.1.1 Default Register Configuration
      2. 4.1.2 Illumination
      3. 4.1.3 Sequence Set
      4. 4.1.4 Degamma Curves
      5. 4.1.5 Image/Video
      6. 4.1.6 Flash Blocks
      7. 4.1.7 Flash Programming
    2. 4.2 DLP Control Program
      1. 4.2.1 Connection
      2. 4.2.2 Scripting
      3. 4.2.3 Registers
      4. 4.2.4 Commands
    3. 4.3 MSP430 Example Code
  6. 5Revision History

4.1.3 Sequence Set

The sequence sets determine the frame rate and duty cycle partition of each RGB color. The recommended frame rate is 25 Hz. Ideally, the duty cycle of the three color (red, green, and blue) would be split equally at 33% each; however, a larger green duty cycle is recommended to achieve a higher brightness output.

For a single color or monochromatic LED, set the duty cycle of a single channel to 100%, and the other two channels to 0%. In the case of the White LED variant of the EVM, the green channel must be used.

GUID-2942AC43-D5B3-4F5E-9246-18A576A2E2F2-low.png Figure 4-3 DLP Composer - Sequence Set

The TI created project will include two sequences: baseline and high brightness. TI recommends using the baseline sequence for optimal color, and only using the high brightness sequence to maximize the lumens output.

The duty cycling of each color is made possible through the use of a multiplexer with active channel selection by the PWM_SEL_0 and PWM_SEL_1 pins of the FPGA. This, in combination with the overall LED driver, PWM of each color, and shunt enable, gives the ability to select different current limits for each of the colors, which is important for color calibration and dimming the image for thermal derating.