DLPU124 june   2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Overview
  5. 2 If You Need Assistance
  6. 3 DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) Overview
    1. 3.1  Welcome
    2. 3.2  DLP LightCrafter DLPC910 Evaluation Module (DLPLCRC910EVM) Hardware
    3. 3.3  DLPLCRC910EVM Board
    4. 3.4  Other Items Needed for Operation
    5. 3.5  DLPLCRC910EVM Connections
    6. 3.6  DLP LightCrafter DLPC910 LEDs
    7. 3.7  Apps FPGA Trigger Input
    8. 3.8  DLPLCRC910EVM HPC FMC Cables
    9. 3.9  DLPLCRC910EVM and DMD EVM Assembly
    10. 3.10 Connecting an Apps FPGA Board to the DLPLCRC910EVM
  7. 4 Quick Start
    1. 4.1 Power-up the DLPLCRC910EVM
    2. 4.2 Power-down the DLPLCRC910EVM
  8. 5 Operating the DLPLCRC910EVM
    1. 5.1 DLPLCRC910EVM GUI and Apps FPGA Software
    2. 5.2 PC Software
      1. 5.2.1 Menu Bar
      2. 5.2.2 Icon Bar
      3. 5.2.3 Main Window
        1. 5.2.3.1 Script Commands sub-window
          1. 5.2.3.1.1 Load Tab
          2. 5.2.3.1.2 Reset Tab
          3. 5.2.3.1.3 Clear Tab
          4. 5.2.3.1.4 Float Tab
          5. 5.2.3.1.5 Control Tab
        2. 5.2.3.2 Script Sub-Window
        3. 5.2.3.3 Status Sub-Window
      4. 5.2.4 DLPC910 Registers
        1. 5.2.4.1 Status/Control Tab
          1. 5.2.4.1.1 Status Items
          2. 5.2.4.1.2 DMD Control Items
          3. 5.2.4.1.3 Design Items
        2. 5.2.4.2 Register List Tab
          1. 5.2.4.2.1  DESTOP_INTERRUPT_CLEAR - 0x0000
          2. 5.2.4.2.2  DESTOP_INTERRUPT_SET - 0x0004
          3. 5.2.4.2.3  DESTOP_INTERRUPT_ENABLE - 0x0008
          4. 5.2.4.2.4  MAIN_STATUS (DLPC910) - 0x000C
          5. 5.2.4.2.5  DESTOP_CAL - 0x0010
          6. 5.2.4.2.6  DESTOP_DMD_ID_REG - 0x0014
          7. 5.2.4.2.7  DESTOP_CATBITS_REG - 0x0018
          8. 5.2.4.2.8  DESTOP_910VERSION_REG - 0x001C
          9. 5.2.4.2.9  DESTOP_RESET_REG - 0x0020
          10. 5.2.4.2.10 DESTOP_INFIFO_STATUS - 0x0024
          11. 5.2.4.2.11 DESTOP_BUS_SWAP - 0x0028
          12. 5.2.4.2.12 DESTOP_DMDCTRL - 0x002C
          13. 5.2.4.2.13 DESTOP_BIT_FLIP - 0x0030
        3. 5.2.4.3 Settings Tab
      5. 5.2.5 Apps FPGA Registers
        1. 5.2.5.1 Status/Control Tab
          1. 5.2.5.1.1 Status Items
          2. 5.2.5.1.2 PBC Control Items
          3. 5.2.5.1.3 Row/Block Operations Items
          4. 5.2.5.1.4 Test Pattern Items
        2. 5.2.5.2 Apps Registers Tab
          1. 5.2.5.2.1  APPS_INTERRUPT_CLEAR - 0x0000
          2. 5.2.5.2.2  APPS_INTERRUPT_SET - 0x0004
          3. 5.2.5.2.3  APPS_INTERRUPT_ENABLE - 0x0008
          4. 5.2.5.2.4  MAIN_STATUS (Apps) - 0x000C
          5. 5.2.5.2.5  APPS_CNTRL - 0x0010
          6. 5.2.5.2.6  APPSTOP_PATTERNSEL - 0x0014
          7. 5.2.5.2.7  APPSTOP_TEST_ROWADDR - 0x0018
          8. 5.2.5.2.8  APPSTOP_LOADER_RESET_TYPE - 0x001C
          9. 5.2.5.2.9  DMD_TYPEREG - 0x0020
          10. 5.2.5.2.10 APPS_BUFFER_WSTART - 0x0024
          11. 5.2.5.2.11 APPS_FIFO_BURST - 0x0028
          12. 5.2.5.2.12 APPS_ROW_CTRL - 0x002C
          13. 5.2.5.2.13 APPS_BLK_CTRL - 0x0030
          14. 5.2.5.2.14 APPS_ROW_LOADER - 0x0034
          15. 5.2.5.2.15 APPS_LOAD_TRIG_INTERVAL - 0x0038
          16. 5.2.5.2.16 APPS_EXPOSE_TIME - 0x003C
          17. 5.2.5.2.17 APPS_LOADER_CTRL - 0x0040
          18. 5.2.5.2.18 APPS_DMD_PARK - 0x0044
          19. 5.2.5.2.19 APPS_EXT_RST_EVT - 0x0048
          20. 5.2.5.2.20 APPS_BUILD_DATE - 0x0080
          21. 5.2.5.2.21 APPS_VERSION - 0x0084
          22. 5.2.5.2.22 APPS_FIXED_ID - 0x0088
          23. 5.2.5.2.23 APPS_GPIF_TEST - 0x008C
    3. 5.3 JTAG Flash Programming
    4. 5.4 SPI Flash Programming
    5. 5.5 AMD Xilinx VC-707 Configuration PROM Programming
    6. 5.6 USB Firmware Programming
  9. 6 Connectors
    1. 6.1  J1 - USB - Micro B USB 2.0 Connector
    2. 6.2  J2 - DLPC910 I2C Connector
    3. 6.3  J4 - PMBUS (I2C) Connector
    4. 6.4  J6 - USB GPIO Connector
    5. 6.5  J8 - 400 Position FMC Connector (Female)
    6. 6.6  J14 - Power (Alternate)
    7. 6.7  J15 - Power
    8. 6.8  J17 - JTAG Boundary Scan Connector
    9. 6.9  J18 - SPI Programming Connector
    10. 6.10 J19, J20, and J21 - Fan Connectors
    11. 6.11 J500, J501 - FMC Connector (Male)
  10. 7 DLPLCRC910EVM Power Supply Requirements
    1. 7.1 External Power Supply Requirements
  11. 8 Related Documentation from Texas Instruments
  12. 9 Abbreviations and Acronyms
  13. 10Safety
    1. 10.1 Caution Labels

3.5 DLPLCRC910EVM Connections

Figure 3-4 depicts the switches and connectors with their respective locations. Note: DMD EVM board, APPS FPGA board, power supply (and cable), and USB cable are NOT included with the module.

GUID-20230326-SS0I-ZGN9-F5LH-PNRFFZQBTSLK-low.svg Figure 3-3 DLPLCRC910EVM Connectors (Top View)
Table 3-1 DLPLCRC910EVM Connector Reference
Connector Reference EVM Function Description or Use
SW1 Apps FPGA Reset Switch Momentary contact switch to reset the Apps FPGA GUI code running on the attached AMD Xilinx VC-707 EVM. When released, the Apps FPGA boots from reset.
SW2 8 Position Apps FPGA Options dip switch Used for selecting Apps FPGA options:
  • SW2_0: MIRROR FLOAT - Mirror Float Enable (Default not enabled = switch OFF)
  • SW2_1: LOAD4_ENZ - Load 4 enable switch. (Default not enabled = switch OFF)
  • SW2_2: COMP_DATA - Compliment Data (Default not enabled = switch ON)
  • SW2_3: NS_FLIP - Top to bottom flip (Default = not enabled switch ON)
  • SW2_4: Not Used (Default = switch ON)
  • SW2_5: Not Used (Default = switch ON)
  • SW2_6: Not Used (Default = switch ON)
  • SW2_7: WDT_ENZ - Watchdog timer enable (Default not enabled = switch ON)
By default, positions 1 and 2 are in the switch "OFF" position [logic 1].
Note: The inputs connected to SW2 are pulled high through a pullup resistor when in the "OFF" position [logic 1] and pulled low when in the "ON" position [logic 0]. Positions 0 and 1 are not enabled when the switch is "OFF" [logic 1] and positions 2, 3, and 7 are not enabled when "ON" [logic 0].
SW3 DMD Park Turning this switch off issues PWR_FLOAT and parks the DMD and stops the DLPC910 logic.
Note: Turn this switch off before disabling power with SW4 and turn this switch on before enabling power with SW4.

Once SW3 is turned off a full power cycle using SW4 is required to restore operation.
SW4 Power Enable Switch Enables Power on the DLPLCRC910EVM.
Note: Turn on SW3 (PWR_FLOAT - DMD Park) before enabling power and turn off SW3 before disabling power.
J1 Micro USB B Connector Connect USB cable from PC running DLPC910 GUI.
J2 External I2C PMBUS I2C connector.
J3 Apps FPGA Test Points 0 - 7 Apps FPGA connected test points:
  • GND: Pin 1
  • APPS_TSTPT7: Pin 2 -Apps FPGA DLPC910 Trigger (input)
  • APPS_TSTPT6: Pin 3 - debounced SW5 push button (output)
  • APPS_TSTPT5: Pin 4 - data enable from apps loader (output)
  • APPS_TSTPT4: Pin 5 - load busy from apps loader (output)
  • APPS_TSTPT3: Pin 6 - mirror settling busy from apps loader (output)
  • APPS_TSTPT2: Pin 7 - trigger from the apps loader (output)
  • APPS_TSTPT1: Pin 8 - mirror reset busy from apps loader (output)
  • APPS_TSTPT0: Pin 9 - mirror reset active signal (output)
  • GND: Pin 10
J4 External PMBUS PMBUS connector for TI development and test only.
J5 Prom address select Prom address select for USB firmware load [default address 001 - not populated; address 011 - populated].
J6 USB GPIO B0 - B7 USB GPIO Header:
  • GND: Pin 1
  • USB GPIO B7: Pin 2
  • USB GPIO B6: Pin 3
  • USB GPIO B5: Pin 4
  • USB GPIO B4: Pin 5
  • USB GPIO B3: Pin 6
  • USB GPIO B2: Pin 7
  • USB GPIO B1: Pin 8
  • USB GPIO B0: Pin 9
  • GND: Pin 10

These pins are available for customer definition or future use.
J7 DCLKIN Speed Selection Pin 1 SPEED_SEL_1 used in conjunction with J11 (SPEED_SEL_0) to select 400 or 480 MHz operation. Routed to Apps FPGA.

Configurations:

  • 400 MHz: J7 and J11 jumpered - DLP6500FLQ, DLP9000X, or DLP9000XUV (default)
  • 480 MHz: J7 jumpered and J11 not jumpered - DLP9000X and DLP9000XUV only
Note: The DLPLCR65FLQEVM does NOT run at 480 MHz.
J8 DMD EVM Board HPC FMC Connector Used to connect a DLPLCR65FLQEVM, DLPLCR90XEVM, or DLPLCR90XUVEVM.
J9 DLPC910 Test Points 8 - 15 DLPC910 connected test points:
  • GND: Pin 1
  • DLPC_TSTPT8: Pin 2
  • DLPC_TSTPT9: Pin 3
  • DLPC_TSTPT10: Pin 4
  • DLPC_TSTPT11: Pin 5
  • DLPC_TSTPT12: Pin 6
  • DLPC_TSTPT13: Pin 7
  • DLPC_TSTPT14: Pin 8
  • DLPC_TSTPT15: Pin 9
  • GND: Pin 10

Reserved for TI internal testing and debug.
J10 DLPC910 I2C Address Selector Jumper Selects the DLPC910 I2C Address:
  • 0x36: Not jumpered (default)
  • 0x34: Jumpered
    Note: If installed, then use the DLPC910 Status/Control Registers Settings page to change the I2C address to operate correctly.
J11 DCLKIN Speed Selection Pin 0 SPEED_SEL_0 used in conjunction with J7 (SPEED_SEL_1) to select 400 or 480 MHz operation. Routed to Apps FPGA.

Configurations:

  • 400 MHz: J7 and J11 jumpered - DLP6500FLQ, DLP9000X, or DLP9000XUV (default)
  • 480 MHz: J7 jumpered and J11 not jumpered - DLP9000X and DLP9000XUV only
Note:

The DLPLCR65FLQEVM does not run at 480 MHz.

Although the DLP9000X and DLP9000XUV run at 400 MHz, only 480 MHz operation has been fully validated.
J12 VSP Enable (no longer used) This jumper is no longer used.
J13 DLPC910 Test Points 0 - 7 DLPC910 connected test points:
  • GND: Pin 1
  • DLPC_TSTPT0: Pin 2
  • DLPC_TSTPT1: Pin 3
  • DLPC_TSTPT2: Pin 4
  • DLPC_TSTPT3: Pin 5
  • DLPC_TSTPT4: Pin 6
  • DLPC_TSTPT5: Pin 7
  • DLPC_TSTPT6: Pin 8
  • DLPC_TSTPT7: Pin 9
  • GND: Pin 10

Reserved for TI internal testing and debug.
J14 +12 VDC 6-Pin Power Connector (Alternate) EVM power alternate input. [Pin 1,2,3 = GND, Pin 4,5,6 = +12 VDC, ] See Section 7.1.
J15 +12 VDC Power input EVM power input. [Pin 1 = +12 VDC, Pin 2,3 = GND] See Section 7.1.
J16 REV_SEL_0 DLPR910 Configuration Prom Revision Selection Jumper. REV_SEL_1 is held low.
  • Not jumpered = 0 (default)
  • Jumpered = 1 - Not Used
J17 JTAG Connector JTAG header for connecting a JTAG programmer to the DLPR910.
J18 Flash Configuration Connector SPI Flash programming connector.
J19, J20, J21 +12 VDC external Fan Connectors 2-pin +12 VDC fan connectors [Pin 1 = GND, Pin 2 = +12 VDC]
J22 Apps FPGA Reset Jumper Jumper 22 prevents SW1 from pulling the Apps FPGA on the attached AMD Xilinx VC-707 EVM into reset.
  • Not jumpered = Allows SW1 to pull the Apps FPGA into reset (default)
  • Jumpered = Prevent SW1 from pulling Apps FPGA into reset
J500 Apps FPGA FMC connector 1 DLPC910 to Apps FPGA and USB parallel interface to the Apps FPGA 400 pin FMC connector.
J501 Apps FPGA FMC connector 2 DLPC910 to the Apps FPGA 400 pin FMC connector.