JAJSBF8B June   2011  – April 2018 TPS54478

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (BOOT) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Slow Start / Tracking Pin
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 START-UP into Prebiased Output
      12. 7.3.12 Synchronize Using the RT/CLK Pin
      13. 7.3.13 Power Good (PWRGD Pin)
      14. 7.3.14 Overvoltage Transient Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small Signal Model for Loop Response
      17. 7.3.17 Simple Small Signal Model for Peak Current Mode Control
      18. 7.3.18 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 Standby Operation
    5. 7.5 Programming
      1. 7.5.1 Sequencing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Slow Start Capacitor
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Output Voltage and Feedback Resistors Selection
        8. 8.2.2.8 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

7.3.8 Slow Start / Tracking Pin

The TPS54478 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow start time. Before the SS pin reaches the voltage threshold VSSTHR, the charge current is about 45 μA. The TPS54478 internal pull-up current source of 2.2 μA charges the external slow start capacitor after the SS pin voltage exceeds VSSTHR. Equation 4 calculates the required slow start capacitor value where Tss is the desired slow start time in ms and Css is the required capacitance in nF.

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Equation 4. TPS54478 eq4_css_lvsas2.gif

If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.21 V, or a thermal shutdown event occurs, the TPS54478 stops switching. When the VIN goes above UVLO, EN is released or pulled high, or a thermal shutdown is exited, then SS/TR is discharged to below 65 mV before reinitiating a powering up sequence. The VSENSE voltage will follow the SS/TR pin voltage with a 65mV offset up to 90% of the internal voltage reference. When the SS/TR voltage is greater than 90% of the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.

TPS54478 startup_lvsas2.gifFigure 23. Sequential Start-Up Sequence
TPS54478 sequencial_lvsas2.gifFigure 24. Sequential Startup using EN and PWRGD
TPS54478 rad_stup_lvsas2.gifFigure 25. Schematic for Ratio-metric Start-Up Sequence
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TPS54478 SS_ratio_lvsas2.gifFigure 26. Ratio-metric Startup

Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 27 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 0.86 V for a complete handoff to the internal voltage reference as shown in Figure 28.

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Equation 5. TPS54478 eq5_r1_lvsas2.gif

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Equation 6. TPS54478 eqB_r2_lvsas2.gif

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TPS54478 ratiosimul_lvsas2.gifFigure 27. Simultaneous Startup Sequence
TPS54478 SSTR_pins_lvsas2.gifFigure 28. Simultaneous Start-Up using Coupled SS/TR Pins