8.2.2.8 Compensation

There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal current mode control, the design equations can be easily simplified. The power stage gain is constant at low frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0 degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole shown in Equation 33.

For the TPS54478 most circuits will have relatively high amounts of slope compensation. As more slope compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the pspice model of SLVM279 apply the values calculated previously to the output filter components of L1, C9, and C10. Set Rload to the appropriate value. For this design, L1 = 1.2 µH. C8 and C9 use the derated capacitance value of 45 µF, and the ESR is set to 3 mΩ. The Rload resistor is 1.8 / 4 = 450 mΩ. Now the power stage characteristic can be plotted as shown in Figure 37.

For this design, the intended crossover frequency is 70 kHz. From the power stage gain and phase plots, the gain at 70 kHz is -12.03 dB and the phase is -131.86 degrees. For 60 degrees of phase margin, additional phase boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at crossover. The required value of R3 can be calculated from Equation 34.

To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 70 kHz. The required value for C5 is given by Equation 35.

To maximize phase gain the high frequency pole is not implemented and C4 is not populated. The pole can be useful to offset the ESR of aluminum electrolytic output capacitors. If desired the value for C4 can be calculated from Equation 36.

For maximum phase boost, the pole frequency F_P will typically be one decade above the intended crossover frequency F_CO.

The feed forward capacitor C10, is used to increase the phase boost at crossover above what is normally available from Type II compensation. It places an additional zero/pole pair located at Equation 37 and Equation 38.

This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well. For optimum performance, the zero and pole should be located symmetrically about the intended crossover frequency. The required value for C10 can calculated from Equation 39.

For this design the calculated values for the compensation components are R3 = 30.6 kΩ ,C5 = 736 pF and C10 = 197 pF. Using standard values, the compensation components are R3 = 30.9 kΩ ,C5 = 820 pF and C10 = 220
pF.