SBAU408 august   2023 ADS7953

 

  1.   1
  2.   ADS7953EVM-PDK Evaluation Module
  3.   Trademarks
  4. 1Overview
    1. 1.1 ADS7953EVM-PDK Features
    2. 1.2 ADS7953EVM Features
  5. 2Analog Interface
    1. 2.1 Connectors for Analog Inputs
    2. 2.2 ADC Input Signal Driver
      1. 2.2.1 Input Signal Path
  6. 3Digital Interfaces
    1. 3.1 SPI for the ADC Digital I/O
  7. 4Power Supplies
    1. 4.1 ADC Voltage Reference Configuration
  8. 5ADS7953EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface Software Installation
  9. 6ADS7953EVM-PDK Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Time Domain Display Tool
    3. 6.3 Spectral Analysis Tool
    4. 6.4 Histogram Analysis Tool
    5. 6.5 Device Configuration
    6. 6.6 Alarm Configuration
  10. 7Schematic, Bill of Materials, and Printed-Circuit Board Layout
    1. 7.1 Schematic
    2. 7.2 Bill of Materials
    3. 7.3 PCB Layout

6.1 EVM GUI Global Settings for ADC Control

Figure 6-2 shows the input parameters of the GUI (and the default values), through which the various functions of the ADS7953EVM-PDK can be exercised. These settings are global and persist across the GUI tools listed in the top left pane (or from one page to another).

GUID-20221007-SS0I-7J2D-Z412-D677PJT9L1VC-low.svgFigure 6-2 EVM GUI Global Input Parameters

The ADS7953 interface configurations can be selected on this page. The GUI lets the user select the ADC input range, mode of operation (manual, Auto 1, and Auto 2), ADC voltage reference, and ADC channel selection using a drop-down menu.

The SCLK Frequency and Sampling Rate settings are selected on this page. The GUI lets the user enter the target values for these two parameters, and the GUI computes the closest value that can be achieved, considering the timing constraints of the device.

Specify a target SCLK frequency (Hz) and the GUI tries to match this frequency as closely as possible by changing the PHI phase-locked loop (PLL) settings; however, the achievable frequency can differ from the target value entered. Similarly, the sampling rate of the ADC can be adjusted by modifying the Target Sampling Rate argument (Hz). The achievable ADC sampling rate can differ from the target value, depending on the applied SCLK frequency and the closest match achievable is displayed. This page, therefore, allows various settings available on the device to be tested in a repetitive fashion until arriving at the best settings for the corresponding test scenario.