SLAAEG6 November   2023 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Summary

3.2 Auto Secondary BCLK Ratio

Secondary ASI needs to be Target, Primary ASI can be either Controller, Target, or disabled Secondary ASI BCLK provided by user is used as Reference clock for the PLL or Audio Root Source clock.

Configurations to enter this mode include

Table 3-3 Register Settings to Setup Mode
Mode Configuration
CLK_SRC_SEL (B0_P0_R52[3:1]) – must be 3’d0
CUSTOM_CLK_CFG register (B0_P0_R50[0]) – must be 1’b0
SASI_SAMP_RATE (B0_P0_R51[7:2])
SASI_FS_BCLK_RATIO {B0_P0_R58[5:0], B0_P0_R59
Must be configured as 0 for the device to auto detect

Controller Mode: To operate primary ASI as Controller Mode, specify the Fs Rate as well as the BCLK to Fs ratio.

Table 3-4 Register Setting to Setup as Controller
Mode Configuration
PASI_MST_CFG B0_P0_R55[4]
1 to operate Primary ASI as Controller 0 to operate Primary ASI as Target (Default)
PASI_FS_BCLK_RATIO B0_P0_R56[5:0], B0_P0_R57
PASI_SAMP_RATE B0_P0_R50[7:2]
FS_MODE B0_P0_R55[0]
Must be configured as 0 for the device to auto detect