SLAAEG6 November 2023 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1
The Device Supports a Primary as well as Secondary ASI. There are several automatic modes of operation described where either the primary BCLK /FYSNC or Secondary BCLK/FSYNC can be used for determination of the incoming timing modes.
In addition, the MCLK / FSYNC can also be used to do the timing determination.
The device has the following interfaces that setup the clocking.
Interface | Setup |
---|---|
MCLK | Master Clock |
FSYNC | Primary FSYNC/ Secondary SYNC |
PASI BCLK | Primary BCLK |
PASI FSYNC | Primary FSYNC |
SASI BCLK | Secondary BCLK |
SASI FSYNC | Secondary SYNC |
The BCLK and FSYNC Pins as well as the GPIO/GPI/GPO pins can be configured to setup the Primary and Secondary ASI.
The timings must lie within the limits described in the following tables.
Pins | Timings |
---|---|
Fs | 3 KHz-768 KHz |
BCLK | 256 KHz - 24.576 MHz |
MCLK | 256 KHz - 49.152 MHz |
Pins | Timings |
---|---|
Fs | 2.75 KHz-705.6 KHz |
BCLK | 235.2 KHz – 22.57 MHz |
MCLK | 235.1 KHz - 45.15 MHz |