SLAAEG6 November   2023 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Summary

3.4 Auto MCLK Fixed

MCLK supplied at the input Pad to be user as audio source, MCLK frequency has no integral relation with the Fsync frequency (PLL use is mandatory) Both Primary and Secondary ASI’s can be only configured as Controller.

Only certain combinations of MCLK Frequencies as given in MCLK_FREQ_SEL register are allowed. The following frequencies for MCLK are allowed.

Table 3-7 Allowed MCLK Frequencies
MCLK_FREQ_SEL Frequency to be provided (MHz)
3’d0 12
3’d1 12.288
3’d2 13
3’d3 16
3’d4 19.2
3’d5 19.68
3’d6 24
3’d7 24.576
Table 3-8 Register Settings to Setup Mode
Mode Configuration
CLK_SRC_SEL (B0_P0_R52[3:1]) – needs to be 3’d4
CUSTOM_CLK_CFG register (B0_P0_R50[0]) – needs to be 1’b0
MCLK_FREQ_SEL register (B0_P0_R55[7:5])
FS_MODE register (B0_P0_R55[0])
Table 3-9 Primary as Controller
Mode Configuration
PASI_MST_CFG B0_P0_R50[7:2]
PASI_FS_BCLK_RATIO B0_P0_R56[5:0], B0_P0_R57
Table 3-10 Secondary as Controller
Mode Configuration
SASI_SAMP_RATE B0_P0_R51[7:2]
PASI_FS_BCLK_RATIO {B0_P0_R58[5:0], B0_P0_R59}

The following menus from Pure Path Console 3 Show this mode.

The MCLK input is setup for a input frequency of 13 Mhz on GPIO1 pin.

The Primary ASI is a Controller. This creates a FSYNC of 48 Khz and BCLK of 6.144 Mhz.