SLUA560D June 2011 – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1

13 Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)

This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. When the converter is operating below 50% load the converter will be operating in valley switching. In order to achieve zero voltage switching on switch node of QB_d, the turn-on (t_ABSET) delays of FETs QA and QB needs to be initially set based on the interaction of L_S and the theoretical switch node capacitance. The following equations are used to set t_ABSET initially.

Equate shim inductance to two times C_OSS capacitance:

Equation 126.

2 π \times f_{R} L_{S} = \frac{1}{2 π \times f_{R} \times (2 \times C_{O S S_Q A_A V G})}

Calculate tank frequency:

Equation 127.

f_{R} = \frac{1}{2 π \sqrt{L_{S} \times (2 \times C_{O S S_Q A_A V G})}}

Set initial t_ABSET delay time and adjust as necessary.

Note:

The 2.25 factor of the t_ABSET equation was derived from empirical test data and may vary based on individual design differences.

Equation 128.

t_{A B S E T} = \frac{2.25}{f_{R} \times 4} \approx 346 n s

The resistor divider formed by R_DA1 and R_DA2 programs the t_ABSET, t_CDSET delay range of the UCC28950/1. Select a standard resistor value for R_DA1.

Note:

t_ABSET can be programmed between 30 ns to 1000 ns.

Equation 129.

R_{D A 1} = 8.25 k Ω

The voltage at the ADEL input of the UCC28950/1 (V_ADEL) needs to be set with R_DA2 based on the following conditions.

If t_ABSET > 155 ns set V_ADEL = 0.2 V, t_ABSET can be programmed between 155 ns and 1000 ns:

If t_ABSET ≤ 155 ns set V_ADEL = 1.8 V, t_ABSET can be programmed between 29 ns and 155 ns:

Based on V_ADEL selection, calculate R_DA2:

Equation 130.

R_{D A 2} = \frac{R_{D A 1} \times V_{A D E L}}{5 V - V_{A D E L}} \approx 344 Ω

Select the closest standard resistor value for R_DA2:

Equation 131.

R_{D A 2} = 348 Ω

Recalculate V_ADEL based on resistor divider selection:

Equation 132.

V_{A D E L} = \frac{5 V \times R_{D A 2}}{R_{D A 1} + R_{D A 2}} = 0.202 V

Resistor R_DELAB programs t_ABSET:

Equation 133.

R_{D E L A B} = \frac{(t_{A B S E T} - 5 n s)}{n s} \times \frac{(0.15 V + V_{A D E L} \times 1.46) \times 1 0^{3}}{5} \times \frac{1}{1 A} \approx 30.4 k Ω

Select a standard resistor value for the design:

Equation 134.

R_{D E L A B} = 30.1 k Ω

Note:

Once you have a prototype up and running it is recommended you fine tune t_ABSET at light load to the peak and valley of the resonance between L_S and the switch node capacitance. In this design the delay was set at 10% load.

Figure 13-1 t_ABSET to Achieve Valley Switching at Light Loads

The initial starting point for the QC and QD turn on delays (t_CDSET) should be initially set for the same delay as the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays (t_CDSET) by properly selecting resistor R_DELCD (Pin 7).

Equation 135.

t_{A B S E T} = t_{C D S E T}

Resistor R_DELCD programs t_CDSET:

Equation 136.

R_{D E L C D} = \frac{(t_{A B S E T} - 5 n s)}{n s} \times \frac{(0.15 V + V_{A D E L} \times 1.46) \times 1 0^{3}}{5} \times \frac{1}{1 A} \approx 30.4 k Ω

Select a standard resistor for the design:

Equation 137.

R_{D E L C D} = 30.1 k Ω

Note:

Once you have a prototype up and running it is recommended to fine tune t_CDSET at light load. In this design the CD node was set to valley switch at roughly 10% load. Obtaining ZVS at lighter loads with switch node QD_d is easier due to the reflected output current present in the primary of the transformer at FET QD and QC turnoff/on. This is because there was more peak current available to energize L_S before this transition, compared to the QA and QB turnoff/on.

Figure 13-2 t_CDSET to Achieve Valley Switching at Light Loads

There is a programmable delay for the turnoff of FET QF after FET QA turnoff (t_AFSET) and the turnoff of FET QE after FET QB turnoff (t_BESET). A good place to set these delays is 50% of t_ABSET. This will ensure that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it will cause OUTE and OUTF not to overlap correctly and it will create excess body diode conduction on FETs QE and QF.

Equation 138.

t_{A F S E T} = t_{B E S E T} = t_{A B S E T} \times 0.5

The resistor divider formed by R_CA1 and R_CA2 programs the t_AFSET and t_BESET delay range of the UCC28950/1. Select a standard resistor value for R_CA1.

Note:

t_EFSET and t_BESET can be programmed between 32 ns to 1100 ns.

Equation 139.

R_{C A 1} = 8.25 k Ω

The voltage at the A_DELEF pin of the UCC28950/1 (V_ADELEF) needs to be set with R_CA2 based on the following conditions.

If t_AFSET < 170 ns set V_ADEL = 0.2 V, t_ABSET can be programmed between 32 ns and 170 ns:

If t_ABSET > or = 170 ns set V_ADEL = 1.7 V, t_ABSET can be programmed between 170 ns and 1100 ns:

Based on V_ADELEF selection, calculate R_CA2:

Equation 140.

R_{C A 2} = \frac{R_{C A 1} \times V_{A D E L E F}}{5 V - V_{A D E L E F}} \approx 4.25 k Ω

Select the closest standard resistor value for R_CA2:

Equation 141.

R_{C A 2} = 4.22 k Ω

Recalculate V_ADELEF based on resistor divider selection:

Equation 142.

V_{A D E L E F} = \frac{5 V \times R_{C A 2}}{R_{C A 1} + R_{C A 2}} = 1.692 V

The following equation was used to program t_AFSET and t_BESET by properly selecting resistor R_DELEF.

Equation 143.

R_{D E L E F} = \frac{(t_{A F S E T} \times 0.5 - 4 n s)}{n s} \times \frac{(2.65 V - V_{A D E L E F} \times 1.32) \times 1 0^{3}}{5} \times \frac{1}{1 A} \approx 14.1 k Ω

A standard resistor was chosen for the design.

Equation 144.

R_{D E L E F} = 14 k Ω

Resistor R_TMIN programs the minimum duty cycle on time (t_MIN) that the UCC28950/1 (Pin 9) can demand before entering burst mode. If the UCC28950/1 controller tries to demand a duty cycle on time of less than t_MIN the power supply will go into burst mode operation. Please see the UCC28950/1 data sheet for details regarding burst mode. For this design we set the minimum on time to 100 ns.

Equation 145.

t_{M I N} = 100 n s

The minimum on time is set by selecting R_TMIN with the following equation.

Equation 146.

R_{T M I N} = 12.1 k Ω

Equation 147.

R_{T M I N} = \frac{(t_{M I N} - 15 n s) \times 1 0^{3}}{6.6 s} \approx 12.9 k Ω

A standard resistor value is then chosen for the design.

Equation 148.

R_{T M I N} = 12.1 k Ω

There is a pin that is provided for setting up the converter switching frequency (Pin 10). The frequency can be selected by adjusting timing resistor R_T.

Equation 149.

R_{T} = (\frac{2.5 \times 1 0^{6} \frac{Ω H z}{V}}{\frac{f_{S}}{2}} - \frac{Ω}{V}) \times (V_{R E F} - 2.5 V) \times 2.5 \times 1 0^{3} \approx 60 k Ω

Select a standard resistor for the design.

Equation 150.

R_{T} = 61.9 k Ω