SLUA963B June   2020  – October 2022 UCC21710-Q1 , UCC21732-Q1 , UCC5870-Q1

 

  1.   HEV/EV Traction Inverter Design Guide Using Isolated IGBT and SiC Gate Drivers
  2. 1Introduction
  3. 2HEV/EV Overview
    1. 2.1 HEV/EV Architectures
    2. 2.2 HEV/EV Traction Inverter System Architecture
    3. 2.3 HEV/EV Traction Inverter System Performance Impact
  4. 3Design of HEV/EV Traction Inverter Drive Stage
    1. 3.1  Introduction to UCC217xx-Q1
    2. 3.2  Designing a Traction Inverter Drive System Using UCC217xx-Q1
    3. 3.3  Description of Protection Features
    4. 3.4  Protection Features of UCC217xx-Q1
    5. 3.5  UCC217xx-Q1 Protection and Monitoring Features Descriptions
      1. 3.5.1 Primary and Secondary Side UVLO and OVLO
      2. 3.5.2 Over-Current (OC) and Desaturation (DESAT) Detection
      3. 3.5.3 2-Level and Soft Turn-Off
      4. 3.5.4 Power Switch Gate Voltage (VGE/VGS) Monitoring
      5. 3.5.5 Power Switch Anti-Shoot-Through
      6. 3.5.6 Integrated Internal or External Miller Clamp
      7. 3.5.7 Isolated Analog-to-PWM Channel
      8. 3.5.8 Short-Circuit Clamping
      9. 3.5.9 Active Pulldown
    6. 3.6  Introduction to UCC5870-Q1
    7. 3.7  Designing a Traction Inverter Drive System Using UCC5870-Q1
    8. 3.8  Description of Protection Features
    9. 3.9  Protection Features of UCC5870-Q1
    10. 3.10 UCC5870-Q1 Protection and Monitoring Features Descriptions
      1. 3.10.1  Primary and Secondary Side UVLO and OVLO
      2. 3.10.2  Programmable Desaturation (DESAT) Detection and Over-Current (OC)
      3. 3.10.3  Adjustable 2-Level or Soft Turn-Off
      4. 3.10.4  Active High-Voltage Clamp
      5. 3.10.5  Power Switch Gate Voltage (VGE/VGS) Monitoring
      6. 3.10.6  Gate Threshold Voltage Monitor
      7. 3.10.7  Power Switch Anti-Shoot-Through
      8. 3.10.8  Active Short Circuit (ASC)
      9. 3.10.9  Integrated Internal or External Miller Clamp
      10. 3.10.10 Isolated Analog-to-Digital Converter
        1. 3.10.10.1 Temperature Monitoring of Power Transistor
      11. 3.10.11 Short-Circuit Clamping
      12. 3.10.12 Active and Passive Pulldown
      13. 3.10.13 Thermal Shutdown and Temperature Warning of Driver IC
      14. 3.10.14 Clock Monitor and CRC
      15. 3.10.15 SPI and Register Data Protection
  5. 4Isolated Bias Supply Architecture
  6. 5Summary
  7. 6References
  8. 7Revision History

3.10.15 SPI and Register Data Protection

SPI input and output data integrity is monitored as well as register data content. This is to ensure proper communications and storage of data for setting driver parameters and functions.

When the UCC5870-Q1 transitions to the ACTIVE state, the contents of configuration and control registers are protected by CRC engine. The configuration CRC is enabled using the proper Configuration bit. The various registers protected by the CRC are outlined in the datasheet. The CRC fault detection is performed every tCRCCFG (typically 1 ms). If the calculated CRC checksum for the configuration registers does not match the CRC checksum calculated upon entering the Active state, Status bits are set and, if unmasked, the nFLT1 output goes low. Additionally, for the secondary side CRC failure, the driver output is forced to the state pre-defined in a Configuration register. Diagnostics for the CRC check are also available. A Control Register can be commanded to induce a CRC error on the primary or secondary side.

The CRC that checks for SPI transfer are continuously updated as SPI traffic is received/sent. The CRC is updated with every 16-bits that are received. In this set of commands, the configuration is updated and compared on that command.

The SDI CRC checksum data is continuously calculated as SPI data frames are received. Once the MCU writes to the to CRC Data Transmission (TX) bits, this triggers a comparison of the data in the CRC TX bits with the internally calculated CRC. Once the comparison is complete, the CRC calculation logic is reset. When there is a mismatch between CRC TX data and CRC calculated internally, the Status bit is set and, if unmasked, the nFLT1 output pulls low and the output is set based on the pre-configured register setting.

The SDO CRC checksum is continuously calculated as data is clocked out of SDO. The resulting CRC is stored in the CRC Receive (RX) Data bits. The bits are updated whenever chip select, nCS, transitions from low to high. The CRC calculation logic is reset when the CRC RX bits are read.

After each power up, the UCC5870-Q1 performs a TRIM CRC check on the internal non-volatile memory on both the primary and secondary sides. If the calculated CRC checksum does not match the CRC checksum stored in the internal TRIM memory, Status bits are set and, if unmasked, the nFLT1 output goes low. Additionally for the secondary side CRC failure, the driver output is forced to the pre-defined state.