Under and over-voltage lockout (UVLO and OVLO) are used to protect the driver IC as well as monitor the voltage used to drive the power switch on the secondary side. UVLO is integrated into UCC217xx-Q1 for both the primary and secondary side supplies, VCC and VDD respectively. These are used to protect the system in case of bias supply failures. The output is pulled low if VCC or VDD drops below the UVLO threshold. Additionally, if there is a UVLO fault, the RDY pin will go HIGH. For VCC the threshold is 2.7 V with a 0.2 V band of hysteresis. The VDD UVLO threshold is 12 V, referenced to COM, with 0.8 V hysteresis. Aside from bias failures, the VDD-side UVLO is beneficial to protect the power switch. Based on the I-V characteristics of high-power IGBTs and SiC MOSFETs, if the device is driven at 12 V the conduction losses are smaller and early saturation of the device can be prevented. In this way, UVLO can be useful to prevent damaging the FET due to a drop in supply voltage.

Overvoltage lockout (OVLO) is also implemented to protect the power switch from being driven with too high of a voltage, outside of the device ratings, which could cause gate oxide breakdown or reduced lifetime. The driver IC should not be supplied with a voltage beyond the maximum ratings, as it may result in driver failure and uncertain driver output state. OLVO is implemented using external circuitry to protect the driver and power device from bias supply failure on the secondary side supply, VDD. VDD is divided down and compared to a fixed voltage reference generated by a Zener diode. When the divided voltage drops below the Zener voltage, the comparator output will switch and will be sent across the isolation barrier to the MCU.

Figure 3-3 Integrated UVLO and External OVLO Implementation