SLUAAM4 December   2023 BQ76905 , BQ76907

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Direct Commands
    1. 1.1 Alarm Enable - 0x66
    2. 1.2 Cell 1 Voltage - 0x14
    3. 1.3 Internal Temperature - 0x28
    4. 1.4 CC2 Current - 0x3A
    5. 1.5 Direct Command Summary
      1. 1.5.1 Disabling Auto Refresh
  5. 2Subcommands
    1. 2.1 DEVICE_NUMBER - 0x0001
    2. 2.2 FET_ENABLE - 0x0022
    3. 2.3 RESET - 0x0012
    4. 2.4 CB_ACTIVE_CELLS - 0x0083
    5. 2.5 Subcommand Summary
  6. 3Reading and Writing RAM Registers
    1. 3.1 Read Enabled Protections A
    2. 3.2 Enter CONFIG_UPDATE Mode
    3. 3.3 Write Enabled Protections A
    4. 3.4 Write VCell Mode
    5. 3.5 Exit CONFIG_UPDATE Mode
    6. 3.6 Reading and Writing RAM Registers Summary
  7. 4I2C With CRC
  8. 5Simple Code Examples
  9. 6References

4 I2C With CRC

The I2C interface on the BQ7690x family includes an optional CRC check. The CRC feature can be enabled in the Settings:Configuration:I2C_Config[CRC] register. If this register is changed while using BQStudio, then BQStudio can be restarted so that it can detect the new communication mode. Two examples follow of I2C waveform captures with the CRC check enabled.

The CRC for the first data byte is computed on all of the bytes after the I2C start up to and including the first data byte. For every data byte after the first byte, the CRC byte is computed for only that byte. In Figure 4-1, using the FET_ENABLE subcommand, the CRC for the first byte is computed for [0x10 0x3E 0x22] - the resulting CRC is 0x63. The CRC for the second byte [0x00] is 0x00.

GUID-1C52FBF3-7CB7-4B53-B95C-1402ED88D43C-low.png Figure 4-1 Captured I2C Waveform for FET_ENABLE Subcommand With CRC

The VCell 1 command is used in Figure 4-2, and the CRC for the first byte is computed for [0x10 0x14 0x11 0xC5]. The resulting CRC is 0x79. The CRC for the second byte [0x0B] is 0x31.

GUID-20230810-SS0I-HHDD-4ZTG-NJHGXKBR063P-low.png Figure 4-2 Captured I2C Waveform for VCell 1 Command With CRC