SLUAAM4 December   2023 BQ76905 , BQ76907

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Direct Commands
    1. 1.1 Alarm Enable - 0x66
    2. 1.2 Cell 1 Voltage - 0x14
    3. 1.3 Internal Temperature - 0x28
    4. 1.4 CC2 Current - 0x3A
    5. 1.5 Direct Command Summary
      1. 1.5.1 Disabling Auto Refresh
  5. 2Subcommands
    1. 2.1 DEVICE_NUMBER - 0x0001
    2. 2.2 FET_ENABLE - 0x0022
    3. 2.3 RESET - 0x0012
    4. 2.4 CB_ACTIVE_CELLS - 0x0083
    5. 2.5 Subcommand Summary
  6. 3Reading and Writing RAM Registers
    1. 3.1 Read Enabled Protections A
    2. 3.2 Enter CONFIG_UPDATE Mode
    3. 3.3 Write Enabled Protections A
    4. 3.4 Write VCell Mode
    5. 3.5 Exit CONFIG_UPDATE Mode
    6. 3.6 Reading and Writing RAM Registers Summary
  7. 4I2C With CRC
  8. 5Simple Code Examples
  9. 6References

2.4 CB_ACTIVE_CELLS - 0x0083

The CB_ACTIVE_CELLS subcommand shown in Table 2-4 is an example of a subcommand that can read or write cell balancing data to a register. When written, balancing starts on the specified cells. In Figure 2-4, cell balancing is performed on cell 1 by writing the 0x0083 command and 0x02 data to 0x3E followed by a write to 0x60/0x61 with the checksum and length. When writing data with subcommands, the checksum and length are necessary for the data to be accepted. The checksum is calculated on the address and data (0x83, 0x00, 0x02) and is the complement of the sum of these bytes. In this case, the checksum is 0x7A. The length includes the two bytes for device address and command address for a total length of 0x05.

Note: The total length must be in hexadecimal format. For example, a block of 10 registers can have a length of 0x0A, not 0x10.
Table 2-4 CB_ACTIVE_CELLS Subcommand Description
Command Name Description
0x0083 CB_ACTIVE_CELLS Cell balancing active cells: When written, starts balancing on the specified cells.
GUID-20220912-SS0I-F12J-NZGH-CX7WG959BTLC-low.png Figure 2-4 Captured I2C Waveform for CB_ACTIVE_CELLS Subcommand