SLUUCU2A March   2023  – September 2023 UCC14130-Q1 , UCC14131-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 U1 Component Selection
    2. 1.2 Pin Configuration and Functions
  5. 2Description
    1. 2.1 EVM Electrical Performance Specifications
  6. 3Schematic
  7. 4EVM Setup and Operation
    1. 4.1 Recommended Test Equipment
    2. 4.2 External Connections for Easy Evaluation
    3. 4.3 Powering the EVM
      1. 4.3.1 Power on for Start-up
      2. 4.3.2 Power off for Shutdown
    4. 4.4 EVM Test Points
    5. 4.5 Probing the EVM
  8. 5Performance Data
    1. 5.1  Efficiency Data
    2. 5.2  Regulation Data
    3. 5.3  Steady State Input Current
    4. 5.4  Start-Up Waveforms
    5. 5.5  Inrush Current
    6. 5.6  AC Ripple Voltage
    7. 5.7  EN and Timing
    8. 5.8  RLIM
    9. 5.9  Shutdown
    10. 5.10 Thermal Performance
  9. 6Assembly and Printed Circuit Board (PCB) Layers
  10. 7Bill of Materials (BOM)
  11. 8Revision History

1.2 Pin Configuration and Functions


GUID-D6662632-C029-4993-AD6C-547B9E42915F-low.svg

Figure 1-1 DWN Package, 36-Pin SSOP (Top View)
Table 1-2 Pin Functions (refer and follow the data sheet)
PINTYPE1DESCRIPTION
NAMENO.
GNDP1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18GPrimary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief.
PG3O

Active low power-good open-drain output pin. PG remains low when (UVLO ≤ VVIN ≤ OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); TJ_Primary ≤ TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSECONDARY_RISE

ENA4IEnable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum.
VIN6, 7PPrimary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect two, parallel, 10-µF ceramic capacitors from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8.
VEE19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36G

Secondary-side reference connection for VDD. The VEE pins are used for the high current return paths.

VDD28, 29PSecondary-side isolated output voltage from transformer. Connect a 10-μF and a parallel 0.1-μF ceramic capacitor from VDD to VEE. The 0.1-μF ceramic capacitor is the high frequency bypass and must be next to the IC pins.
RLIM32PSecondary-side second isolated output voltage resistor to limit the source current from VDD.
FBVEE33IFeedback output voltage sense pin used to adjust the output voltage.
FBVDD34IFeedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back layer connected with vias.
VEEA35GSecondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin.
(1) P = power, G = ground, I = input, O = output