3 Symmetrical Footprint

The symmetrical butterfly layout with equal amounts of input capacitors on each side of the package is designed to function with minimal ringing on the SW-node. The recommended BOM layout is included in the default TPS54KB20 EVM, retaining equal amounts of capacitors on each side of the input. These proportional components make sure smaller amounts of SW-node and VIN-SW ringing are present when the device is actively switching under rated operating conditions. The low side and high side MOSFETS have proven to display smaller amounts of ringing on SW-node and VIN-SW when the default symmetrical EVM is tested.

Figure 3-1 depicts the recommended symmetrical schematic for TPS54KB20. Capacitors C21, C23, C37, and C39 have been prematurely removed as a result of the symmetrical EVM. The data provided is taken under the symmetrical TPS54KB20 EVM conditions using the capacitors shown in Figure 3-1.

Figure 3-2 and Figure 3-3 are illustrated to represent the EVM symmetrical board layout with the recommended amount of input capacitors present.